Engineering topics
Publications and source records attributed to Tripon-Canseliet, Charlotte.
We designed and fabricated a fix-tuned balanced frequency tripler working in the 260-340 GHz band to be the first stage of a x3x3x3 multiplier chain to 2.7 THz. The design of a dual-chip version of this multiplier featuring an input splitter / output combiner as part of the input / output matching networks of both chips - with no degradation of the expected bandwidth and efficiency- will be presented.
We report on the fabrication at the Jet Propulsion Laboratory of a fixed-tuned split-block waveguide balanced frequency tripler working in the 260-340 GHz band. This tripler will be the first stage of a x3x3x3 multiplier chain to 2.7 THz (the last stages of which are being fabricated at JPL) and is therefore optimized for high power operation. The multiplier features six GaAs Schottky planar diodes in a balanced configuration integrated on a GaAs membrane. Special attention was put on splitting the input power as evenly as possible among the diodes in order to ensure that no diode is overdriven. Preliminary RF tests indicate that the multiplier covers the expected bandwidth and that the efficiency is in the range 1.5-7.5 % with 100 mW of input power.
We report on the design and performance of a fix-tuned x2x 3x 3 frequency multiplier chain that covers 1.55-1.75 THz. The chain is nominally pumped with 100 mW at W-band. At 120 K the measured output power is larger than 4 (mu)W across the band with a peak power of 100 (mu) W at 1.665 THz. A similar chain operated at room temperature produced a peak power of 21 (mu)W. These power levels now make it possible to deploy multipixel heterodyne imaging arrays in this frequency range.
We report on the design and performance of a broad-band, high-power 540-640-GHz fix-tuned balanced frequency tripler chip that utilizes four planar Schottky anodes. The suspended strip-line circuit is fabricated with a 12-micron-thick support frame and is mounted in a split waveguide block. The chip is supported by thick beam leads that are also used to provide precise RF grounding. At room temperature, the tripler delivers 0.9-1.8 mW across the band with an estimated efficiency of 4.5%-9%. When cooled to 120 K, the tripler provides 2.0-4.2 mW across the band with an estimated efficiency of 8%-12%.
We report on the design methodology of fix-tuned split-block waveguide balanced frequency triplers working at 300,600 and 900 GHz. They feature four to six GaAs Schottky planar diodes in a balanced configuration. A 6-anode 300 GHz tripler, a 6-anode 560 GHz tripler and a 4-anode 900 GHz tripler will be fabricated with JPL membrane technology in order to minimize dielectric loading and ensure accurate thickness of the substrate. A 4-anode 600 GHz tripler was fabricated with JPL substrateless technology that delivers 0.8-1.6mW in the 540-640 GHz band at room temperature. When cooled to l2OK this tripler delivers 2-4mW from 540 to 640 GHz.
We report on the design of a fix-tuned split-block waveguide balanced frequency tripler working nominally at 900GHz. It uses a GaAs Schottky planar diode pair in a balanced configuration. The circuit will be fabricated with JPL membrane technology in order to minimize dielectric loading. The multiplier is bias-less to dramatically ease the mounting and the operating procedure. At room temperature, the expected output power is 50- 130 (micro)W in the band 800-970 GHz when the tripler is pumped with 4mW. By modifying the waveguide input and output matching circuit, the multiplier can be tuned to operate at lower frequencies.
We report on the design methodology of a fix-tuned split-block waveguide balanced frequency tripler working nominally at 300 GHz. It features six GaAs Schottky planar diodes in a balanced configuration. The circuit will be fabricated with JPL membrane technology in order to minimize dielectric loading and insure an accurate and uniform thickness of the substrate. The multiplier power handling is limited by the breakdown voltage of the diodes that depends on the doping level of the active layer. With six diodes, the current choice for the doping level leads to medium power handling capabilities of about 50 mW. Increasing the number of diodes to eight would be an option but would lead to increased difficulties in design and fabrication.