Engineering topics
Stoica, A.
Publications and source records attributed to Stoica, A..
Conceptual Design of the Lunar Crater Radio Telescope (LCRT) on the Far Side of the Moon
In this paper, we present the conceptual design of a Lunar Crater Radio Telescope (LCRT) on the far side of the Moon. We propose to deploy a wire mesh using wall-climbing DuAxel robots in a 3–5 km diameter lunar crater on the farside, with a suitable depth-to-diameter ratio, to form a parabolic reflector with a 1 km diameter. LCRT will be the largest filled-aperture radio telescope in the Solar System. LCRT could enable scientific discoveries in the field of cosmology by observing the early Universe in the 10–50 m wavelength band (i.e., 6-–30 MHz frequency band), which has not been explored for cosmological observations to date. We have described LCRT’s science objectives and key technology challenges, that we need to overcome to make this concept a reality. We envisage that LCRT will open a new window for humanity’s exploration of the Universe.
TransFormers for Ensuring Long-Term Operations in Lunar Extreme Environments
"Surviving Extreme Space Environments" (EE) is one of NASA's Space Technology Grand Challenges. Power generation and thermal control are the key survival ingredients that allow a robotic explorer to cope with the EE using resources available to it, for example, by harvesting the local solar energy or by utilizing an onboard radioisotope thermoelectric generator (RTG). TransFormers (TFs) are a new technology concept designed to transform a localized area within a harsh extreme environment into a survivable micro-environment by projecting energy to the precise location where robots or humans operate. For example, TFs placed at a location on the rim of Shackleton Crater, which is illuminated by solar radiation for most of the year, would be able to reflect solar energy onto robots operating in the dark cold crater. TFs utilize a shape transformation mechanism to un-fold from a compact volume to a large reflective surface, and to control how much-and where-the energy is projected, and by adjusting for the changing position of the sun. TFs would enable in-situ resource utilization (ISRU) activities within locations of high interest that would normally be unreachable because of their extreme environment
Transistor Level Circuit Experiments using Evolvable Hardware
The Jet Propulsion Laboratory (JPL) performs research in fault tolerant, long life, and space survivable electronics for the National Aeronautics and Space Administration (NASA). With that focus, JPL has been involved in Evolvable Hardware (EHW) technology research for the past several years. We have advanced the technology not only by simulation and evolution experiments, but also by designing, fabricating, and evolving a variety of transistor-based analog and digital circuits at the chip level. EHW refers to self-configuration of electronic hardware by evolutionary/genetic search mechanisms, thereby maintaining existing functionality in the presence of degradations due to aging, temperature, and radiation. In addition, EHW has the capability to reconfigure itself for new functionality when required for mission changes or encountered opportunities. Evolution experiments are performed using a genetic algorithm running on a DSP as the reconfiguration mechanism and controlling the evolvable hardware mounted on a self-contained circuit board. Rapid reconfiguration allows convergence to circuit solutions in the order of seconds. The paper illustrates hardware evolution results of electronic circuits and their ability to perform under 230 C temperature as well as radiations of up to 250 kRad.
Taking evolutionary circuit design from experimentation to implementation: some useful techniques and a silicon demonstration
Current techniques in evolutionary synthesis of analogue and digital circuits designed at transistor level have focused on achieving the desired functional response, without paying sufficient attention to issues needed for a practical implementation of the resulting solution. No silicon fabrication of circuits with topologies designed by evolution has been done before, leaving open questions on the feasibility of the evolutionary circuit design approach, as well as on how high-performance, robust, or portable such designs could be when implemented in hardware. It is argued that moving from evolutionary 'design-for experimentation' to 'design-for-implementation' requires, beyond inclusion in the fitness function of measures indicative of circuit evaluation factors such as power consumption and robustness to temperature variations, the addition of certain evaluation techniques that are not common in conventional design. Several such techniques that were found to be useful in evolving designs for implementation are presented; some are general, and some are particular to the problem domain of transistor-level logic design, used here as a target application. The example used here is a multifunction NAND/NOR logic gate circuit, for which evolution obtained a creative circuit topology more compact than what has been achieved by multiplexing a NAND and a NOR gate. The circuit was fabricated in a 0.5 mum CMOS technology and silicon tests showed good correspondence with the simulations.
Speed enhancement with soft computing hardware
We will review our work on electronic neural networks and evolvable hardware to bring out speed advantage.
On-chip evolutionary synthesis of reconfigurable analog computing circuits
The paper presents a Field Programmable Transistor Array (FPTA), developed as an experimental platform for implementing flexible, reconfigurable analog computing.
Scalability issues in evolutionary synthesis of electronic circuits: lessons learned and challenges ahead
This paper describes scalability issues of evolutionary-driven automatic synthesis of electronic circuits. The article begins by reviewing the concepts of circuit evolution and discussing the limitations of this technique when trying to achieve more complex systems.
Development of consistent equivalent models by mixed-model search
This paper introduces a new approach to the development of equivalent models. Models of various accuracy and simulation speed may be needed in different contexts of design and analysis, or within different simulators.
Rapid evolution of analog circuits configured on a field programmable transistor array
The purpose of this paper is to illustrate evolution of analog circuits on a stand-alone board-level evolvable system (SABLES). SABLES is part of an effort to achieve integrated evolvable systems. SABLES provides autonomous, fast (tens to hundreds of seconds), on-chip circuit evolution involving about 100,000 circuit evaluations. Its main components are a JPL Field Programmable Transistor Array (FPTA) chip used as transistor-level reconfigurable hardware, and a TI DSP that implements the evolutionary algorithm controlling the FPTA reconfiguration. The paper details an example of evolution on SABLES and points out to certain transient and memory effects that affect the stability of solutions obtained reusing the same piece of hardware for rapid testing of individuals during evolution.
Evolvable, reconfigurable hardware for future space systems
This paper overviews Evolvable Hardware (EHW) technology, examining its potential for enhancing survivability and flexibility of future space systems. EHW refers to selfconfiguration of electronic hardware by evolutionary/genetic search mechanisms. Evolvable Hardware can maintain existing functionality in the presence of faults and degradations due to aging, temperature and radiation. It can also configure itself for new functionality when required for mission changes or encountered opportunities. The paper illustrates hardware evolution in silicon using a JPL-designed programmable device reconfigurable at transistor level as the platform and a genetic algorithm running on a DSP as the reconfiguration mechanism. Rapid reconfiguration allows convergence to circuit solutions in the order of seconds. The experiments demonstrate functional recovery from faults as well as from degradation at extreme temperatures indicating the possibility of expanding the operational range of extreme electronics through evolved circuit solutions.
Evolving circuits in seconds: experiments with a stand-alone board-level evolvable system
The purpose of this paper is twofold: first, to illustrate a stand-alone board-level evolvable system (SABLES) and its performance, and second to illustrate some problems that occur during evolution with real hardware in the loop, or when the intention of the user is not completely reflected in the fitness function.
On two new trends in evolvable hardware: employment of HDL-based structuring, and design of multi-functional circuits
This paper comments on some directions of growth for evolvable hardware, proposes research directions that address the scalability problem and gives examples of results in novel areas approached by EHW.
An evolvable hardware platform based on DSP and FPTA
We describe in this paper the rationale and design of an evovlable hardware platform based on the use of a stand-alone processor and a Field Programable Transistor Array.