Engineering topics
Statman, J.
Publications and source records attributed to Statman, J..
Standardization of TT&C Systems to Reduce Operations Cost - Case Study
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Deep Space Network Revitalization - Operations For the 21st Century
The National Aeronautics and Space Administration (NASA) supports unmanned space missions through a Deep Space Network (DSN) that is developed and operated by the Jet Propulsion Labortory (JPL) and its subcontractors.
Inter Continental, Inter-Agency Arraying - The Galileo Experience
Since November 1, 1996, the Galileo orbital tour of jupiter and its moons is routinely supported by a massive array of large antennas: two 70-meter antennas in GDSCC and CDSCC, a 64-meter antenna at Parkes, and additional 34-meter antennas at CDSCC. The scope of this array is unprevented, it operates daily in a routine fashion, inter-continentally, and employs antennas of several agenscies, namely two complexes of JPL's Deep Space Network (DSN) an CSIRO's Parkes facility. The Success of this routine arraying operation is the basis for the DSN's new array of 34-meter antennas that is being implementet at GDSCC.
Signal-to-noise ratio losses in full spectrum combining of signals with a downconverted subcarrier
This article presents the results of the signal-to-noise ratio loss in the process of full spectrum combining of signals with a downconverted subcarrier under imperfect conditions. These imperfect conditions not only include the misalignment of the carrier, the subcarrier, and the symbols, but they also include the nonideal filtering in the subcarrier downconversion process, the cutoff of the data bandwidth, and the distortion in signal waveform.
Symbol signal-to-noise ratio loss in square-wave subcarrier downconversion
This article presents the simulated results of the signal-to-noise ratio (SNR) loss in the process of a square-wave subcarrier down conversion. In a previous article, the SNR degradation was evaluated at the output of the down converter based on the signal and noise power change. Unlike in the previous article, the SNR loss is defined here as the difference between the actual and theoretical symbol SNR's for the same symbol-error rate at the output of the symbol matched filter. The results show that an average SNR loss of 0.3 dB can be achieved with tenth-order infinite impulse response (IIR) filters. This loss is a 0.2-dB increase over the SNR degradation in the previous analysis where neither the signal distortion nor the symbol detector was considered.
SNR degradation in square-wave subcarrier downconversion
This article presents a study of signal-to-noise ratio (SNR) degradation in the process of square-wave subcarrier downconversion. The study shows three factors that contribute to the SNR degradation: the cutoff of the higher frequency components in the data, the approximation of a square wave with a finite number of harmonics, and nonideal filtering. Both analytical and simulation results are presented.
Bandwidth compression of noisy signals with square-wave subcarrier
This article discusses a method for downconverting the square-wave subcarrier of spacecraft signals, such as the one from Galileo, which results in a compression bandwidth that lowers the sample rate significantly. The study is focused on three issues. The first is the selection of an adequate down-mixing signal for the resulting signal to have a format similar to that of the original signal, except at a lower subcarrier frequency. The second is the control of the noise level so that the signal to noise ratio is not degraded due to the downconversion. The third is to determine the bandwidth of the downconverted signal considering the uncertainty of the residual carrier frequency.
Large-Constraint-Length, Fast Viterbi Decoder
Scheme for efficient interconnection makes VLSI design feasible. Concept for fast Viterbi decoder provides for processing of convolutional codes of constraint length K up to 15 and rates of 1/2 to 1/6. Fully parallel (but bit-serial) architecture developed for decoder of K = 7 implemented in single dedicated VLSI circuit chip. Contains six major functional blocks. VLSI circuits perform branch metric computations, add-compare-select operations, and then store decisions in traceback memory. Traceback processor reads appropriate memory locations and puts out decoded bits. Used as building block for decoders of larger K.
Big Viterbi Decoder (BVD) results for (7,1/2) convolutional code
The Big Viterbi Decoder (BVD), capable of decoding convolutional codes with constraint lengths of up to 15, is under development for the Deep Space Network (DSN). As part of the development, a commercial single-chip (7,1/2) Viterbi decoder is used to enable early start of system integration. Tests of the integrated partial system (including simulator, input systems, output interfaces, and computer controls) were recently completed at the DSN Compatibility Test Area (CTA-21) at JPL. The system elements used for the demonstration and test results are described.
Wiring Viterbi decoders (splitting deBruijn graphs)
A new Viterbi decoder, capable of decoding convolutional codes with constraint lengths up to 15, is under development for the Deep Space Network (DSN). A key feature of this decoder is a two-level partitioning of the Viterbi state diagram into identical subgraphs. The larger subgraphs correspond to circuit boards, while the smaller subgraphs correspond to Very Large Scale Integration (VLSI) chips. The full decoder is built from identical boards, which in turn are built from identical chips. The resulting system is modular and hierarchical. The decoder is easy to implement, test, and repair because it uses a single VLSI chip design and a single board design. The partitioning is completely general in the sense that an appropriate number of boards or chips may be wired together to implement a Viterbi decoder of any size greater than or equal to the size of the module.
A comparison of methods for DPLL loop filter design
Four design methodologies for loop filters for a class of digital phase-locked loops (DPLLs) are presented. The first design maps an optimum analog filter into the digital domain; the second approach designs a filter that minimizes in discrete time weighted combination of the variance of the phase error due to noise and the sum square of the deterministic phase error component; the third method uses Kalman filter estimation theory to design a filter composed of a least squares fading memory estimator and a predictor. The last design relies on classical theory, including rules for the design of compensators. Linear analysis is used throughout the article to compare different designs, and includes stability, steady state performance and transient behavior of the loops. Design methodology is not critical when the loop update rate can be made high relative to loop bandwidth, as the performance approaches that of continuous time. For low update rates, however, the miminization method is significantly superior to the other methods.