Fractional delay filter for a digital signal processing system
A processing element for implementation in a digital signal processing system is provided. The processing element is configured to receive a first data stream comprising a plurality of digital values where each value represents a sample of an analog signal. The processing element is further configured to receive a second data stream comprising a series of digital values where each value represents a sample of the analog signal. The processing element is configured to filter the first data stream via a first Farrow-structured fractional delay (FD) filter and output a filtered first data stream; filter the second data stream via a second Farrow-structured FD filter and output a filtered second data stream; and temporarily store values from the second data stream and output the stored values to the first Farrow-structured FD filter so that the stored values can be used to filter the first data stream.