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Sheldon, Doug

Publications and source records attributed to Sheldon, Doug.

Cold Survivable Distributed Motor Controller (CSDMC)

This paper presents the results of NASA’s COLDTECH development entitled “Cold Survivable Distributed Motor Controller (CSDMC)”. This work addresses the need to lower the mass, power and volume of the motor control electronics and its associated cabling. Landed payload mass of ocean world missions typically requires a spacecraft launch mass of 7-10x the landed mass due to the required propellant to get the payload to the surface. Reduction of landed mass leads to cheaper, more frequent missions and/or increased science return. This work addresses this need by developing a distributed electronics architecture, which places control and power electronics near or at actuators and instruments. The outcome of this effort will result in a 10X reduction in harness mass, enabling a significant increase in science payload which then enables more capable sample acquisition, delivery and analysis systems on these missions. Placing the control and power conversion electronics at or near the actuators or instruments is the cornerstone of our distributed architecture. To do this, we developed the technology necessary to distribute the electronics and place them on a shared interface and power bus. This enables a significant reduction in cable mass along with its associated complexity. This allows spacecraft designers to take advantage of volume at the extremities that would normally not be utilized. In this paper we discuss the technologies and system design to achieve these goals in support of ocean world missions. These technologies include the development of our motor control modules, a point of load regulator and isolated converter modules along with the packaging technology necessary to allow our electronics to survive the extreme temperatures.

Stell, Chris

Compact Low Power Avionics for the Europa Lander Concept and Other Missions to Ocean Worlds

This paper presents the results of NASA’s Game Changing Technology development entitled “Ultra Low Temperature Electronics” and ColdTech technology effort entitled “Cold Survivable Distributed Motor Controller”. The purpose of these back-to-back projects is to address the Command & Data Handling (CDH), Power and Motor Control needs for missions to ocean worlds such as the potential Europa Lander project. We addressed the mass reduction challenge by developing the key technologies necessary to design a next generation compact motor control avionics. The project’s goal is to allow a Europa Lander to last longer on the surface and provide more room for additional science by reducing the volume, mass and power of its avionics and the amount of energy required to keep the avionics warm.

Suh, Jong-ook

Compact Low Power Avionics for the Europa Lander Concept and Other Missions to Ocean Worlds

This paper presents the results of NASA’s game-changing technology development entitled “Ultra Low Temperature Electronics” which represents a paradigm shift in spacecraft avionics development. The project has developed compact avionics technologies to address the Command & Data Handling (CDH), Power and Motor Control needs for mission concepts to ocean worlds such as a potential Europa Lander. We addressed this need by developing the key technologies necessary to develop a next generation compact avionics package. The key technologies that we developed significantly reduce the size, weight, power, and cost (SWAP-C) of the avionics package. These technologies will also allow extreme-environment missions to last longer in their environment by reducing the power and energy requirement to keep the avionics warm.

Bolotin, Gary

Increasing Small Satellite Reliability- A Public-Private Initiative

At present, CubeSat components and buses are generally not appropriate for missions where significant risk of failure, or the inability to quantify risk or confidence, is acceptable. However, in the future we anticipate that CubeSats will be used for missions requiring reliability of 1-3 years for Earth-observing missions and even longer for Planetary, Heliophysics, and Astrophysics missions. Their growing potential utility is driving an interagency effort to improve and quantify CubeSat reliability, and more generally, small satellite mission risk. The Small Satellite Reliability Initiative (SSRI)—an ongoing activity with broad collaborative participation from civil, DoD, and commercial space systems providers and stakeholders—targets this challenge. The Initiative seeks to define implementable and broadly-accepted approaches to achieve reliability and acceptable risk postures associated with several SmallSat mission risk classes—from “do no harm” missions, to those associated with missions whose failure would result in loss or delay of key national objectives. These approaches will maintain, to the extent practical, cost efficiencies associated with small satellite missions and consider constraints associated with supply chain elements, as appropriate. The SSRI addresses this challenge from two architectural levels—the mission- or system-level, and the component- or subsystem-level. The mission- or system-level scope targets assessment approaches that are efficient and effective, with mitigation strategies that facilitate resiliency to mission or system anomalies while the component- or subsystem-level scope addresses the challenge at lower architectural levels. The initiative does not limit strategies and approaches to proven and traditional methodologies, but is focused on fomenting thought on novel and innovative solutions. This paper discusses the genesis of and drivers for this initiative, how the public-private collaboration is being executed, findings and recommendations derived to date, and next steps towards broadening small satellite mission potential.

SmallSat

Impact of Negative Bias Temperature Instability on FPGAs

In this sliide presentation the statistical impact of PMOS Negative Bias Temperature Instability (NBTI) degradation on circuit delay is reviewed. An on-board timing circuitry that was been developed to detect and measure timing delays in SRAM-based LUT commercial FPGAs is described. The initial experimental data on the on-board timing circuit are reviewed.

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