A comprehensive study of the impact of dislocation loops on leakage currents in Si shallow junction devices
In this work, the electrical properties of dislocation loops and their role in the generation of leakage currents in p-n or Schottky junctions were investigated both experimentally and through simulations. Deep Level Transient Spectroscopy (DLTS) reveals that the implantation of silicon with 2 × 10{sup 15} Ge cm{sup −2} and annealing between 1000 °C and 1100 °C introduced two broad electron levels E{sub C} − 0.38 eV and E{sub C} − 0.29 eV in n-type samples and a single broad hole trap E{sub V} + 0.25 eV in the p-type samples. These trap levels are related to the extended defects (dislocation loops) formed during annealing. Dislocation loops are responsible for the significant increase of leakage currents which are attributed to the same energy levels. The comparison between structural defect parameters and electrical defect concentrations indicates that atoms located on the loop perimeter are the likely sources of the measured DLTS signals. The combined use of defect models and recently developed DLTS simulation allows reducing the number of assumptions and fitting parameters needed for the simulation of leakage currents, therefore improving their predictability. It is found that simulations based on the coupled-defect-levels model reproduce well the measured leakage current values and their field dependence behaviour, indicating that leakage currents can be successfully simulated on the exclusive basis of the experimentally observed energy levels.