Engineering topics
Publications and source records attributed to Safdari, Murtaza.
This poster shows the experiment and access system as it will be installed in the MINOS shaft, along with important connecting components such as the atom sources and connection nodes.
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The ETROC2 prototype for CMS MTD Endcap Timing Layer (ETL) upgrade 520__ $$aThe Endcap Timing ReadOut Chip (ETROC) is designed to process LGAD signals with time resolution down to about 40-50ps per hit. The ETROC2 is the first full size (16x16) prototype design with the front-end based on and scaled up from the ETROC1 (4x4). The readout designs at pixel and global level and the system interfaces are all new and are compatible with the final chip specifications in terms of functionality. The ETROC2 is intended as a learning chip, as a stepstone to the ETROC3 which is intended as the pre-production design. The ETROC2 design and test results will be presented.
The Endcap Timing ReadOut Chip (ETROC) for the Compact Muon Solenoid (CMS) Minimum ionizing particle Timing Detector (MTD) is designed to process Low Gain Avalanche Diode (LGAD) signals with a time resolution of 40-50ps per hit, with 30-35 ps per charged particle using two layer detector. The ETROC2, is the first full size (16x16 pixels) and full functionally design that has been tested in hadron and electron beams at CERN and DESY (Sep 2023 - June 2024). Precision timing studies at these test beams are done using a self-referential beam telescope composed of up to 4 layers/chips. This talk describes the ETROC2 beam telescope and summarizes the performance of the ETROC2 chips bump-bonded to (16x16) Fondazione Bruno Kessler (FBK) and Hamamatsu Photonics K.K. (HPK) LGAD sensors using results from recent test beams. The experiences and lessons learned during the course of these test beams are also detailed in this talk.
A flexible self-certifying pixel readout test system for testing the Endcap Timing Read-Out Chip (ETROC) has been developed for the CMS MIP Timing Detector (MTD), part of the upgrade for the HL-LHC. The system includes an FPGA-based (Xilinx KC705) test system that can take data from an emulator or up to four ETROC boards in telescope mode. A python based DAQ system simplifies configuration, calibration, and testing of the chips. The system provides an efficient & reliable solution for testing ETROC (ETROC2 since April 2023 with 16x16 pixels, full-size, full functionality prototype) and can be extended to other readout chips with similar architecture (AIDA integration is currently being explored).
The Endcap Timing ReadOut Chip (ETROC) is designed to process LGAD signals with time resolution down to about 40-50ps per hit. The ETROC2 is the first full size (16x16) prototype design with the front-end based on and scaled up from the ETROC1 (4x4). The readout designs at pixel and global level and the system interfaces are all new and are compatible with the final chip specifications in terms of functionality. The ETROC2 is intended as a learning chip, as a stepstone to the ETROC3 which is intended as the pre-production design. The ETROC2 design and test results will be presented.
MAGIS-100 is a next-generation quantum sensor under construction at Fermilab that aims to explore fundamental physics with atom interferometry over a 100 m baseline. This novel detector will search for ultralight dark matter, test quantum mechanics in new regimes, and serve as a technology pathfinder for future gravitational wave detectors in a previously unexplored frequency band. It combines techniques demonstrated in state-of-the-art 10-meter-scale atom interferometers with the latest technological advances of the world’s best atomic clocks. MAGIS-100 will provide a development platform for a future kilometer-scale detector that would be sufficiently sensitive to detect gravitational waves from known sources. Here we present the science case for the MAGIS concept, review the operating principles of the detector, describe the instrument design, and study the detector systematics.