Engineering topics

Russo, Lucas

Publications and source records attributed to Russo, Lucas.

5 records

DOE OSTI2023

Event Fanout/Receiver (evfr) v1.0

The event fanout-receiver is an event-based timing system implementation capable of synchronizing (with respect to clock, events and triggers) to an upstream event generator. This can be used in 2 modes: fanout or receiver. the first one receives 1 upstream timing streams and fanouts it to 36. The second one receives and decodes the stream. This has been in use by ALS for many years and this is a similar implementation, but providing a more flexible configuration

Russo, Lucas↗

DOE OSTI2022

Direct-Sampling Beam Position Monitor (dsbpm) v1.0

Direct-Sampling Beam Position Monitor is an FPGA gateware and embedded firmware that run on evaluation kits (either Xilinx ZCU111 or Xilinx ZCU208 ) that digitizes signals up to 4GSPS and 4GHz analog bandwidth, which can be synchronized to the accelerator timing system, providing synchronous sampling frequency/phase digitization. In addition to these capabilities, a proof of concept for a beam position monitor is also present, providing an envelope detection algorithm capable of determining the transverse beam position for an electron circular accelerator, such as ALS/ALS-U.

Norum, William↗

DOE OSTI2022

Bantamweight Badger UDP support (BWUDP) v1.0

Software networking library to allow an FPGA ethernet core (such as Badger: https://gitlab.lbl.gov/hdl-libraries/bedrock/-/tree/master/badger) to be used in a soft-core processor or microcontroller.

Russo, Lucas↗

DOE OSTI2022

Dual Event Generator (dual-evg) v1.0

The dual event generator is a event-based timing system implementation capable of synchronizing (with respect to clock, events and triggers) hundreds of downstreams devices. This has been in use by ALS for many years and this is a similar implementation, but with a synchronized dual-master frequency , as opposed to just one in a more conventional approach.

Russo, Lucas↗

DOE OSTI2022

High Speed Digitizer Firmware (HSD) v1.0

The High Speed Digitizer firmware is an FPGA gateware and embedded firmware that run on evaluation kits (either Xilinx ZCU111 or Xilinx ZCU208 ) that digitizes signals up to 4GSPS and 4GHz analog bandwidth, which can be synchronized to the accelerator timing system, providing synchronous sampling frequency/phase digitization. In addition to these capabilities, a proof of concept for a beam position monitor is also present, providing an envelope detection algorithm capable of determining the transverse beam position for an electron circular accelerator, such as ALS/ALS-U.

Norum, William↗