A split accumulation gate architecture for silicon MOS quantum dots.
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Engineering topics
Publications and source records attributed to Rudolph, Martin.
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Recently, a single atom transistor was deterministically fabricated using phosphorus in Si by H-desorption lithography with a scanning tunneling microscope (STM). This milestone in precision, achieved by operating the STM in the conventional tunneling mode, typically utilizes slow (∼102 nm2/s) patterning speeds. By contrast, using the STM in a high-voltage (>10 V) field-emission mode, patterning speeds can be increased by orders of magnitude to ≳104 nm2/s. We show that the rapid patterning negligibly affects the functionality of relatively large micron-sized features, which act as contacting pads for these devices. For nanoscale structures, we show that the resulting electrical transport is consistent with the donor incorporation chemistry constraining the electrical dimensions to a scale of 10 nm even though the pattering spot size is 40 nm.
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