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Rubinov, Paul [Fermilab]

Publications and source records attributed to Rubinov, Paul [Fermilab].

4 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2026

Graphical User Interface for a Biasing Board for the PSEC6

The PSEC6 is an application-specific integrated circuit (ASIC) designed for a readout system for a large area picosecond photodetector (LAPPD). The PSEC6 is currently in fabrication and pending testing. The testing system for the PSEC5, the previous iteration of the ASIC, required expensive and non-portable equipment, because the ASIC needs twelve adjustable reference voltages. The new testing system consists of an low-cost, open-source, cross-platform graphical user interface (GUI), a digital system, and a biasing board. The digital system is the interface between the GUI and biasing board, and can be implemented on a microcontroller or field-programmable gate array (FPGA). The biasing board contains twelve digital-to-analog converters (DACs) that are configurable via the GUI, which gives users the ability to write voltage values to all or specific DACs. The GUI was developed in C on Linux using the widget library GTK4 and cross-compiled for Windows compatibility. I2C and SPI protocols were implemented on an Adafruit Feather ESP32-S3 microcontroller to write commands to the DACs and PSEC6. A hardware implementation of the I2C protocol is in development on an FPGA. Since LAPPDs will be used by the Accelerator Neutrino Neutron Interaction Experiment (ANNIE) at Fermilab, the PSEC6 testing system in this internship project can potentially benefit future neutrino research. The project is relevant to the Department of Energy’s microelectronics mission, because the PSEC6 is an ASIC that will handle fast time signals arriving from the detector for readout. It also provided experience with building a cross-platform user interface, practicing digital design and implementation in hardware description language (HDL), and using simulations to inform new design iterations.

Guerrero, Sasha Camila [North Central Coll.]↗
DOE OSTI2026

DAMSA Experiment Conceptual Design White Paper

DAMSA (DArk Messenger Searches at an Accelerator) is a novel short-baseline accelerator experiment aimed at probing short-lived physics processes, including searches for evidence of a dark sector of particle physics and well-motivated Standard Model signals. Motivated by open questions in neutrino physics and the absence of conclusive evidence for conventional weakly interacting massive particles, DAMSA targets MeV-to-sub-GeV dark-sector messengers with feeble couplings that can be produced in abundance at the PIP-II LINAC. By employing an ultra-short baseline of order one meter, DAMSA is uniquely positioned to overcome the beam-dump "ceiling" that limits sensitivity to promptly decaying particles in longer-baseline experiments. The conceptual design emphasizes a beam-dump production scheme combined with a compact detector optimized for rare decays while mitigating intense neutron-induced backgrounds inherent to high-power proton beams. To validate the experimental strategy and detector technologies, the Little DAMSA Path-Finder (LDPF) proof-of-concept experiment is proposed, focusing on axion-like particles decaying to two photons and operating with 300 MeV electron beams at FAST. Successful realization of LDPF will establish the feasibility of the DAMSA approach, enabling a broad and powerful program to explore short-lived new physics and precision Standard Model processes in a previously inaccessible regime. This conceptual design document outlines the technical details of DAMSA's physics goals, the beam facility proposals, key experimental challenges and how to overcome them, and the proposed experimental staging campaigns.

Bhattarai, Prithak [Texas U., Arlington]↗
DOE OSTI2025

Physical Testing of The PSEC5 ASIC

The PSEC5 ASIC is a high-speed waveform sampling chip designed for ultra-fast timing detectors, offering up to 40 GSPS sampling with 10-bit resolution. This makes it well-suited for applications requiring fine time resolution, such as MCPs and LGADs. This work focuses on the physical testing and validation of the chip s internal clocking and SPI-controlled registers. Testing began with inspection of schematics and the prototype to identify and resolve design issues. Then, custom firmware was developed for an Arduino controller to interface with the chip via SPI, enabling read and write access to key control registers. Results confirm that the VCO operates between ~3.2 4.0 GHz and remains stable under non-VCOVDD fluctuations. The Division Ratio register enables frequency division by known factors (256, 128, 64, etc.), indicating a pre-division frequency of 3.2 GHz when the digital band is unmodified. While most registers responded correctly, some issues were observed, including unexpected current draw and unstable discriminator behavior. Overall, the chip shows promising functionality, but further work is needed to understand the state of the read only registers and address the existing issues. Continued testing and firmware development will be critical to ensuring reliable integration into detector systems.

Fahey, Alexander [Unlisted, US]↗