Engineering topics
Publications and source records attributed to Rentsch, Edward M..
Improvement in genlock subsystem consists in incorporation of controllable delay circuit into path of composite synchronization signal obtained from external video source. Delay circuit helps to eliminate potential jitter in video display and ensures setup requirements for digital timing circuits of video camera satisfied.
In proposed interline-transfer timing scheme for charge-coupled-device (CCD) video imaging array, charges accumulated during some fraction of frame period swept out and dumped to prevent overloading and saturation in intensely illuminated photosites. Excess charges swept out at highest possible rate, while charges used for imaging read out at rate lower but was highest rate that provides complete transfer of charge on array and handled by subsequent signal-processing equipment.