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Prokop, N. F.

Publications and source records attributed to Prokop, N. F..

Patch Plate Materials Compatibility Assessment

Lunar dust proved to be a greater problem during the Apollo missions than was originally anticipated. The highly angular, charged dust particles stuck to seals, radiators, and visors; clogged mechanisms; and abraded space suits. As reported by Apollo 12 astronaut Pete Conrad "We must have had more than a hundred hours suited work with the same equipment, and the wear was not as bad on the training suits as it is on these flight suits in just the eight hours we were out.". Dust clinging to surfaces was also transport-ed into habitable spaces leading to lung and eye irritation of the astronauts. The Apollo astronauts were on the Lunar surface less than 24 hours and experienced many dust related problems. With the Artemis program, we are planning longer stays on the surface, with more activities that have the potential to put the astronauts and equipment in contact with greater quantities of Lunar dust. The success of these missions will depend on our understanding of material interactions with Lunar dust and the development of ways to mitigate dust effects in cases where exposure to dust will lead to failure of components, unacceptable loss of power or thermal control, unacceptable loss of visibility, or health issues. Through the Lunar Surface In-novation Initiative (LSII), we are initiating a Patch Plate Materials Compatibility Assessment project. The overall goal of the three year project is to develop passive approaches to mitigate Lunar dust adhesion to surfaces for technologies that are currently at TRL levels 2-3 to bring them to TRL level 5 through ground-based assessment, culminating in a demonstration flight experiment on a Commercial Lunar Payload Services (CLPS) lander in 2022-2023. This paper discusses the detailed technical objectives and approach for this project. References: Gaier, J.R. "The Effects of Lunar Dust on EVA Systems During the Apollo Missions," NASA/TM-2005-213610/REV1, (2005), Apollo 12 Technical Crew Debriefing, December 1, 1969, pp. 10-54.

Miller, S. K. R.

Assessment of Durable SiC JFET Technology for +600 C to -125 C Integrated Circuit Operation

Electrical characteristics and circuit design considerations for prototype 6H-SiC JFET integrated circuits (ICs) operating over the broad temperature range of -125 C to +600 C are described. Strategic implementation of circuits with transistors and resistors in the same 6H-SiC n-channel layer enabled ICs with nearly temperature-independent functionality to be achieved. The frequency performance of the circuits declined at temperatures increasingly below or above room temperature, roughly corresponding to the change in 6H-SiC n-channel resistance arising from incomplete carrier ionization at low temperature and decreased electron mobility at high temperature. In addition to very broad temperature functionality, these simple digital and analog demonstration integrated circuits successfully operated with little change in functional characteristics over the course of thousands of hours at 500 C before experiencing interconnect-related failures. With appropriate further development, these initial results establish a new technology foundation for realizing durable 500 C ICs for combustion engine sensing and control, deep-well drilling, and other harsh-environment applications.

Neudeck, P. G.