Engineering topics
Publications and source records attributed to Pitts, E. R..
Standard Transistor Array (STAR) design system is semicustom approach to generating random-logic integrated MOS digital circuits. Primary program in STAR system is CAPSTAR, STAR Cell Arrangement Program. CAPSTAR is augmented by automatic routining program, Display program and library of logic cells.
Program converts cell-net data into logic-gate models for use in test and simulation programs. Input consists of either Place, Route, and Fold (PRF) or Place-and-Route-in-Two-Dimensions (PR2D) layout data deck. Output consists of either Test Pattern Generator (TPG) or Logic-Simulation (LOGSIM) logic circuitry data deck. Designer needs to build only logic-gate-model circuit description since program acts as translator. Language is FORTRAN IV.
Portions of the Computer Aided Design and Test system, a collection of Large Scale Integrated (LSI) circuit design programs were modified and upgraded. Major modifications were made to the Mask Analysis Program in the form of additional operating commands and file processing options. Modifications were also made to the Artwork Interactive Design System to correct some deficiencies in the original program as well as to add several new command features related to improving the response of AIDS when dealing with large files. The remaining work was concerned with updating various programs within CADAT to incorporate the silicon on sapphire silicon gate technology.
The primary purpose of TPG interface (TPGITF) software is to create test patterns, according to a mathematical model, for a real device. In order for the device actually to be tested or to be accurately simulated, a means is required to transform the TPGITF generated test into forms acceptable as input to logic test equipment or to a software logic simulator. The MACRODATA-200 Logic Test System and the LOGSIM logic simulator are the particular systems supported by the TPGITF software. A description is presented of the TPGITF software processor. It is assumed that the reader is familiar with the TPG, LOGSIM, and TOIL systems. Flow charts are given.
The DJANAL (DisJunct ANALyzer) Program provides a means for the LSI designer to format output from the Mask Analysis Program (MAP) for input to the FETLOG (FETSIM/LOGSIM) processor. This document presents a brief description of the operation of DJANAL and provides comprehensive instruction for its use.
Information is presented for the use of NTRAN (Network TRANslator), a program written in FORTRAN that provides a means for generating input files for the LOGSIM and LASAR programs from PRF and PR2D input decks. The program technical description, input instructions, and deck setup instructions for the Sigma 5 computer, are presented to familiarize the reader with the software.