Engineering topics
Publications and source records attributed to Pellish, Jonathan.
This presentation provides an overview of single event effects in FPGA devices 2015-2016 including commercial Xilinx V5 heavy ion accelerated testing, Xilinx Kintex-7 heavy ion accelerated testing, mitigation study, and investigation of various types of triple modular redundancy (TMR) for commercial SRAM based FPGAs.
We present an independent investigation of heavy-ion single event effect data for the Microsemi RTG4 field programmable gate array (FPGA).
This presentation provides an overview of single event effects in FPGA devices 2015-2016 including commercial Xilinx V5 heavy ion accelerated testing, Xilinx Kintex-7 heavy ion accelerated testing. Mitigation study, and investigation of various types of triple modular redundancy (TMR) for commercial SRAM based FPGAs.
We present the challenges that arise when using redundant clock domains due to their clock-skew. Radiation data show that a singular clock domain (DTMR) provides an improved TMR methodology for SRAM-based FPGAs over redundant clocks.
In the space surrounding Earth there exists an active radiation environment consisting mostly of electrons and protons that have been trapped by Earths magnetic field. This radiation, also known as the Van Allen Belts, has the potential to damage man-made satellites in orbit; thus, proper precautions must be taken to shield NASA assets from this phenomenon. Data on the Van Allen Belts has been collected continuously by a multitude of space-based instruments since the beginning of space exploration. Subsequently, using theory to fill in the gaps in the collected data, computer models have been developed that take in the orbital information of a hypothetical mission and output the expected particle fluence and flux for that orbit. However, as new versions of the modeling system are released, users are left wondering how the new version differs from the old. Therefore, we performed a comparison of three different editions of the modeling system: AE8/AP8 (legacy), which is included in the model 9 graphical user interface as an option for ones calculations, AE9/AP9, and the Space Environment Information System (SPENVIS), which is an online-based form of AE8/AP8 developed by NASA and the European Space Agency that changed the code to allow the program to extrapolate data to predict fluence and flux at higher energies. Although this evaluation is still ongoing, it is predicted that the model 8 (legacy) and SPENVIS version will have identical outputs with the exception of the extended energy levels from SPENVIS, while model 9 will provide different fluences than model 8 based on additional magnetic field descriptions and on-orbit data.
It has been shown that, when exposed to radiation environments, each Field Programmable Gate Array (FPGA) device has unique error signatures. Subsequently, fail-safe and mitigation strategies will differ per FPGA type. In this session several design approaches for safe systems will be presented. It will also explore the benefits and limitations of several mitigation techniques. The intention of the presentation is to provide information regarding FPGA types, their susceptibilities, and proven fail-safe strategies; so that users can select appropriate mitigation and perform the required trade for system insertion. The presentation will describe three types of FPGA devices and their susceptibilities in radiation environments.
This presentation provides an overview of single event effects in FPGA devices 2014-2015 including commercial Xilinx V5 heavy ion accelerated testing, Xilinx Kintex-7 heavy ion accelerated testing. Mitigation study, and investigation of various types of triple modular redundancy (TMR) for commercial SRAM based FPGAs.
This is an independent study to determine the single event destructive and transient susceptibility of the Xilinx Virtex-5QV (SIRF) device. A framework for evaluating complex digital systems targeted for harsh radiation environments such as space is presented.
No abstract available
We present a novel method of FPGA TID testing that measures propagation delay between flip-flops operating at maximum speed. Measurement is performed on-chip at-speed and provides a key design metric when building system-critical synchronous designs.
This report presents total ionizing dose evaluation data for the Linear Technology Corporation LTC1877 high efficiency monolithic synchronous step-down regulator. Data sheet parameters were tracked as a function of ionizing dose up to a total of 20 krad(SiO2). Control devices were also used.
This is a course on SEE Test Plan development. It is an introductory discussion of the items that go into planning an SEE test that should complement the SEE test methodology used. Material will only cover heavy ion SEE testing and not proton, LASER, or other though many of the discussed items may be applicable. While standards and guidelines for how-to perform single event effects (SEE) testing have existed almost since the first cyclotron testing, guidance on the development of SEE test plans has not been as easy to find. In this section of the short course, we attempt to rectify this lack. We consider the approach outlined here as a "living" document: mission specific constraints and new technology related issues always need to be taken into account. We note that we will use the term "test planning" in the context of those items being included in a test plan.
We present results on heavy-ion and proton irradiations for commercial SiGe BiCMOS operational amplifiers: LTC6400-20 from Linear Technology and THS4304 from Texas Instruments. We found that the devices are susceptible to heavy-ion-induced SETs. The SET cross-sections increase with increasing operating frequency. The LTC6400 exhibits a LET(sub th) < 7.4 MeV·sq cm/mg for frequencies ranging from 10 to 1000 MHz. The THS4304 exhibits a LET(sub th) < 4.4 MeV·sq cm/mg at 200 MHz; the LET(sub th) decreases with increasing frequency. The significance of the SETs also increases with frequency. The SETs at 1000 MHz can erase several signal cycles. We al.so found that the LTC6400 is relatively robust against 198 and 54 MeV protons. We did not observe angular sensitivity from the proton irradiations.
Field programmable gate arrays (FPGA) are used in every space application. Currently, most space flight applications use radiation hardened (RH) FPGAs, which are very expensive. There is a desire to use cheaper, commercial off the shelf reprogrammable FPGAs, which are more susceptible to radiation effects known as single-event effects (SEE). The RH parts have SEE and total ionizing dose (TID) hardened elements pre-integrated into the part. This means that the designer does not need to implement any hardening techniques while configuring the device. The COTS parts on the other hand must be mitigated by design in order to insure any form of mitigation. The design techniques this project examines concern the use of localized triple modular redundancy (LTMR) and distributed triple modular redundancy (DTMR). LTMR triples every flip flop in the device architecture while DTMR triples everything except for the global routes (clocks, resets, and enables). The testing was performed on a ProASIC3E FPGA at the Texas A&M cyclotron facility. Two design architectures were used: shift registers and counters, both with LTMR and DTMR mitigation techniques. The test results prove that DTMR is more effective at reducing SEE than LTMR. We also determined that there was not a significant difference between the use of shift registers and counters for test purposes. More testing is required to obtain additional linear energy transfer values for each architecture and mitigation technique in order to determine the most cost-effective method of SEE mitigation.
Radiation requirements and trends. TID: 1) >90% of NASA applications are < 100 krads-Si in piecepart requirements. a) Many commercial devices (NVM and SDRAMs) meet or come close to this. b) Charge pump TID tolerance has improved an order magnitude over the last 10 years. 2) There are always a few programs with higher level needs and, of course, defense needs SEL: 1) Prefer none or rates that are considered low risk. a) Latent damage is a bear to deal with. 2) As we re packing cells tighter and even with lower Vdd, we re seeing SEL on commercial devices regularly (<90nm). a) Often in power conversion, I/O, or control areas. SEU: 1) It s not the bit errors, it s the SEFIs errors that are the biggest issues. a) Scrubbing concerns for risk, power, speed.