Engineering topics
Publications and source records attributed to Pain, B..
Charge-Coupled Device (CCD) based star trackes provide reliable attitude estimation onboard most 3 axis stabilized spacecraft. The spacecraft attitude is calculated based on observed positions of stars, which are located and identified in a CCD image of the sky.
A complete programmable digital camera-on-a-chip based on low power active pixel sensor technology is implemented as a single CMOS integrated circuit.
A CMOS imaging sensor is described that uses active pixel sensor (APS) technology which permits the integration of the detector array with on-chip timing, control and signal chain electronics. This sensor has been used to implement a CMOS APS camera-on-a-chip.
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In the decades since the advent of in situ plasma measurements on board spacecraft, the instrumentation has grown bigger, heavier, and more complex as our understanding of space plasmas improves and our appetite for more information increases...There has thus been a recent interest in the miniaturization of both spacecraft and the instrument payload... This paper describes the results and status of an ongoing design study to understand the problems and trade space of fully integrating an instrument into a micro-spacecraft.
JPL, under sponsorship from the NASA Office of Advanced Concepts and Technology, has been developing a second-generation solid-state image sensor technology. Charge-coupled devices (CCD) are a well-established first generation image sensor technology. For both commercial and NASA applications, CCDs have numerous shortcomings. In response, the active pixel sensor (APS) technology has been under research. The major advantages of APS technology are the ability to integrate on-chip timing, control, signal-processing and analog-to-digital converter functions, reduced sensitivity to radiation effects, low power operation, and random access readout.
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This paper describes ongoing research and development of CMOS active pixel image sensors for low cost commercial applications. A number of sensor designs have been fabricated and tested in both p-well and n-well technologies. Major elements in the development of the sensor include on-chip analog signal processing circuits for the reduction of fixed pattern noise, on-chip timing and control circuits and on-chip analog-to-digital conversion (ADC). Recent results and continuing efforts in these areas will be presented.
This paper presents approaches for on-focal-plane analog-to-digital conversion (ADC). Common approaches and architectures for ADC and their utility for on-focal-plane integration are discussed. Candidate approaches are analyzed with respect to required amplifier gain, bandwidth, capacitance matching, noise and offsets as a function of ADC resolution. A column-parallel ADC architecture appears to be an effective compromise of chip area, power, circuit speed and ADC resolution. The discussion is valid for both infrared focal-plane arrays (FPAs) and visible image sensors.
Recent research results regarding the investigation of CMOS active pixel image sensors (APS) are reported. An investigation of various designs for the pixel, including photogate devices of various geometries and photodiode devices has been performed. Opto-electronic performance including intra-pixel photoresponse maps taken using a focused laser scanning apparatus are presented. Several imaging arrays have also been investigated. A 128 x 128 image sensor has been fabricated and characterized. Both p-well and n-well implementations have been explored. The demonstrated arrays use 2 micron CMOS design rules and have a 40 x 40 micron pixel pitch.
The paper discusses the implementation and analysis of a correlated triple sampling circuit using analog subtractor/integrators. The software and test setup for noise measurements are also described. The correlation circuitry is part of the signal chain for a 256-element InSb line array used in the Visible and Infrared Mapping Spectrometer. Using a focal-plane array (FPA) simulator, system noise measurements of 0.7 DN are obtained. A test setup for FPA/SPE (signal processing electronics) characterization along with noise measurements is demonstrated.