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Moreira, Paulo

Publications and source records attributed to Moreira, Paulo.

6 records
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DOE OSTI2024

First test results of the HGCAL concentrator ASICs: ECON-T and ECON-D

With over 6 million channels, the High Granularity Calorimeter for the CMS HL-LHC upgrade presents a unique data transmission challenge. The ECON ASICs provide a critical stage of on-detector data compression and selection for the trigger path (ECON-T) and data acquisition path (ECON-D) of the HGCAL. The ASICs, fabricated in 65 nm CMOS, are radiation tolerant up to 200 Mrad and require low power consumption: < 2.5 mW/sensor-channel per chip. Here, we report on the first functionality and radiation tests for the ECON-D-P1 full-functionality prototype. We present a comparison of single event effect (SEE) cross sections measured for different methods of triple modular redundancy using test results from the ECON-T-P1 full-functionality prototype.

47 OTHER INSTRUMENTATION↗
DOE OSTI2023

CMS High Granularity Calorimeter ECON-D ASIC overview and radiation testing results

The Compact Muon Solenoid (CMS) Experiment’s High Granularity Calorimeter (HGCAL) upgrade replaces the CMS electromagnetic and hadronic endcap calorimeters in preparation for the high-rate and high-radiation environment of the High Luminosity LHC. To effectively use the over 6 million channels of this highly-segmented “imaging” calorimeter, CMS is pioneering very front-end data compression with the Endcap Concentrator (ECON) ASICs – the ECON-T for the trigger path and the ECON-D for the data path. These 65 nm CMOS ASICs are radiation tolerant (200 Mrad) and low-power (< 2.5 mW/channel). In June 2023, we received the first full-functionality prototype of the data path concentrator ASIC, the ECON-D-P1. This talk will present an overview of the ECON-D-P1, summarize functionality and system testing, and present results from both Total Ionizing Dose (TID) and Single Event Effect (SEE) testing campaigns completed in summer 2023, validating the ECON-D radiation tolerant performance.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2017

A Compact Low-Power Driver Array for VCSELs in 65-nm CMOS Technology

This article presents a compact low-power 4 x 10 Gb/s quad-driver module for Vertical-Cavity Surface-Emitting Laser (VCSEL) arrays in a 65 nm CMOS technology. The side-by-side drivers can be directly wire bonded to the VCSEL diode array, supporting up to 4 channels. To increase the bandwidth of the driver, an internal feed-forward path is added for pole-zero cancellation, without increasing the power consumption. An edge-configurable pre-emphasis technique is proposed to achieve high bandwidth and minimize the asymmetry of the fall and rise times of the driver output current. Measurement results demonstrate a RMS jitter of 0.68 ps for 10 Gb/s operation. Tests demonstrate negligible crosstalk between channels. Under irradiation, the modulation amplitude degrades less than 5% up to 300 Mrad ionizing dose. Finally, the area of the quaddriver array is 500 μm by 1000 μm and the total power consumption for the entire driver array chip is 130 mW for the typical current setting.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2016

10-Gb/s Distributed Amplifier-Based VCSEL Driver IC With ESD Protection in 130-nm CMOS

Here, this paper presents a low-power 10-Gb/s vertical cavity surface emitting laser (VCSEL) driver integrated circuit (IC) with electrostatic discharge (ESD) protection in the 130-nm CMOS technology. A distributed amplifier (DA)-based modulator is proposed to boost the driver bandwidth. It employs artificial transmission lines to cancel the device parasitic capacitances of the driver. A distributed ESD protection technique is applied to equalize the group delay of the DA to optimize the jitter performance. To minimize the silicon area, the optimal number of DA taps in the proposed modulator has been derived. To compensate for the capacitive load and the channel losses at the output of the driver, a frequency-domain preemphasis scheme is proposed. The proposed DA modulator occupies an area of 0.69 mm 2 , and the entire driver IC has a die size of 2 mm×2 mm, including the pads. Both electrical and optical tests have been carried out to characterize the performance of the proposed VCSEL driver IC. Measurements at a data rate of 10-Gb/s demonstrate a typical power consumption of 85 mW under a single 2.5 V supply voltage (49 mW, if separate 1.2 and 2.5 V supplies are used) and an rms jitter of 0.63 and 1.12 ps for the electrical test and optical test, respectively.

24 POWER TRANSMISSION AND DISTRIBUTION↗