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Michael J Krasowski

Publications and source records attributed to Michael J Krasowski.

11 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS2023

Venus Surface Environmental Chamber Test of SiC JFET-R Multi-Chip Circuit Board

This poster describes a first attempt to demonstrate a multi-chip prototype lander control and sensor signal digitization electronics circuit board comprised of ten NASA Glenn IC Generation 11 SiC JFET-R IC chips in 460 °C, 9.4 MPa harsh Venus surface conditions. The lander circuit ceased electrical operation prematurely at 107 °C as the Venus chamber heated up. Optical and SEM post-test inspections indicate fatal dielectric cracks occurred on only one of the ten SiC chips.

silicon carbide↗
NASA NTRS2021

A Saltation Sensor for the Martian Aqueous Habitat Reconnaissance Suite (MAHRS)

Wind-blown sand, otherwise known as saltation, occurs on the surface of Mars, but its characteristics are poorly understood due to insufficient data (Kok, 2010). Space-qualified instrumentation for acquiring saltation data is unavailable, making it difficult to advance our knowledge in this area. Consequently, a saltation sensor probe with supporting electronics was designed and constructed with a clear path to space readiness in order to support future science missions to the Martian surface for advancing the understanding of Martian saltation.

Saltation Sensor↗
NASA NTRS2021

Practical SiC JFET-R Analog Integrated Circuit Design for Extreme Environment Applications

Silicon carbide (SiC) junction field effect transistor and SiC resistor (SiC JFET-R) integrated circuits(ICs) have uniquely demonstrated prolonged operation above 450 °C that promises significant operational improvements to a variety of NASA missions. However, the SiC epiwafers used to fabricate these ICs suffer from epi-growth process immaturity that imparts large and systematic spreads in JFET threshold voltages as a function of the device distance from the center on the wafer. Furthermore, the unprecedently wide range of intended application operating temperatures (in many cases over 600 °C wide) imparts as much as 5-fold change in JFET bias currents. This Technical Memorandum documents methods by which both temperature and radius associated JFET electrical parameter variances can be adequately eliminated, or even exploited in JFET-R circuit designs. Full analog circuit examples, including operational amplifiers, and SPICE simulations across experimentally documented SiC JFET parameter extremes are given to illustrate the efficacy of these methods. The reader may use the examples in this memorandum as either an end point, to get a desired analog signal conditioning design into hardware implemented in SiC JFET-R ICs, or as a basis point from which to derive further improvement.

Michael J Krasowski↗
NASA NTRS2016

Processing and Characterization of Thousand-Hour 500 C Durable 4H-SiC JFET Integrated Circuits

This work reports fabrication and testing of integrated circuits (ICs) with two levels of interconnect that consistently achieve greater than 1000 hours of stable electrical operation at 500 C in air ambient. These ICs are based on 4H-SiC junction field effect transistor (JFET) technology that integrates hafnium ohmic contacts with TaSi2 interconnects and SiO2 and Si3N4 dielectric layers over 1-m scale vertical topology. Following initial burn-in, important circuit parameters remain stable for more than 1000 hours of 500 C operational testing. These results advance the technology foundation for realizing long-term durable 500 C ICs with increased functional capability for sensing and control combustion engine, planetary, deep-well drilling, and other harsh-environment applications.

JFET↗
NASA NTRSDate not supplied

Upscaling of 500 °C Durable SiC JFET-R Integrated Circuits

At HiTEC2018, NASA Glenn Research Center reported the first demonstration of yearlong 500°C operation of ceramic-packaged “Generation 10” ~200-transistor integrated circuits (ICs) based on two-level interconnect silicon carbide (4H-SiC) junction field effect transistors and resistors (JFET-R). This HiTEC 2021submissionupdateson-going efforts at NASA Glenn spanning two subsequent prototype IC generations “11 and 12” to increase both complexity and durability of these ICs. Increased chip complexities of around 1000 transistors/chip for Gen. 11and near 3000 transistors/chip for Gen. 12 aremade possibleby reductions in minimum layout feature sizes (including resistorwidth shrinkage from 6 μm to 2μm) coupled with enlarged die size (from 3x3 mm to 5x5mm). Gen. 11 ICs electrically tested to date include an 8-bit delta-sigma analog to digital converter (ADC) as well as upscaled random access memory (RAM)and nearly 1 kbit read only memory (ROM). However, Gen. 11 prototype ICs exhibited significantly lower yield and durability than Gen. 10 ICs. Development of revised processing is being investigated towards mitigating these issues in subsequentGen. 12 fabrication runcurrentlyin progress.

Silicon Carbide↗
NASA NTRSDate not supplied

Upscaling of 500 °C Durable SiC JFET-R Integrated Circuits

At HiTEC 2018, NASA Glenn Research Center reported the first demonstration of yearlong 500 °C operation of ceramic-packaged “Generation 10” ~200-transistor integrated circuits (ICs) based on two-level interconnect silicon carbide (4H-SiC) junction field effect transistors and resistors (JFET-R). This HiTEC 2021 submission updates on-going efforts at NASA Glenn spanning two subsequent prototype IC generations “11 and 12” to increase both complexity and durability of these ICs. Increased chip complexities of around 1000 transistors/chip for Gen. 11 and near 3000 transistors/chip for Gen. 12 are made possible by reductions in minimum layout feature sizes (including resistor width shrinkage from 6 µm to 2 µm) coupled with enlarged die size (from 3 x 3 mm to 5 x 5 mm). Gen. 11 ICs electrically tested to date include an 8-bit delta-sigma analog to digital converter (ADC) as well as upscaled random access memory (RAM) and nearly 1 kbit read only memory (ROM). However, Gen. 11 prototype ICs exhibited significantly lower yield and durability than Gen. 10 ICs. Development of revised processing is being investigated towards mitigating these issues in subsequent Gen. 12 fabrication run currently in progress.

silicon carbide↗
NASA NTRSDate not supplied

Photovoltaic Investigation on the Lunar Surface (PILS): Design Considerations and Ground Testing

The PILS (Photovoltaic Investigation on the Lunar Surface) platform consists of flight demonstrations of multiple solar cell technologies that could be used for future lunar missions. It also includes a solar charging experiment to shape design considerations of high voltage solar arrays on the Moon that could power in-situ resource utilization systems and other lunar surface assets. This poster and conference proceedings describe the design considerations of the PILS platform and ground testing performed prior to spacecraft integration. The platform is expected to operate on the lunar surface at Lacus Mortis in late 2022.

photovoltaics↗
NASA NTRSDate not supplied

Passive Cooling for Mercury Surface Lander Electronics

A significant barrier to operation of a mission on the surface of Mercury is the temperature. At Mercury’s perihelion distance of 0.313 AU, the solar intensity is 10.6 times the solar flux at Earth orbit, and at the subsolar point, the maximum surface temperature reaches 427°C. For a mission landing on the surface of Mercury at latitude of 40°S, we analyzed using passive thermal control to reduce the temperature of the critical electronics to within the operation temperature limits of silicon devices. The thermal control requires reducing the thermal conductance and infrared flux from the high temperature surface and surrounding spacecraft, and moderating the solar heat input using a surface coating with high solar reflectivity, and maximizing thermal cooling with high infrared emissivity. Using this approach, we find that we can passively cool an electronics box to a temperature of 393K (120°C) using a radiator-white surface with solar absorptivity 0.11 and infrared emissivity 0.91. This temperature is well under 175C target we use for the limits of high-temperature silicon integrated circuits, including RAM and microcontrollers. We could further reduce this operating temperature to as low as 321K (48°C) with an advanced thermal coating, a temperature well within the operational limits of conventional electronics.

Mercury↗
NASA NTRSDate not supplied

Passive Cooling for Mercury Surface Lander Electronics

A significant barrier to operation of a mission on the surface of Mercury is the temperature. At Mercury’s perihelion distance of 0.313 AU, the solar intensity is 10.6 times the solar flux at Earth orbit, and at the subsolar point, the maximum surface temperature reaches 427°C. For a mission landing on the surface of Mercury at latitude of 40°S, we analyzed using passive thermal control to reduce the temperature of the critical electronics to within the operation temperature limits of silicon devices. The thermal control requires reducing the thermal conductance and infrared flux from the high temperature surface and surrounding spacecraft, and moderating the solar heat input using a surface coating with high solar reflectivity, and maximizing thermal cooling with high infrared emissivity. Using this approach, we find that we can passively cool an electronics box to a temperature of 393K (120°C) using a radiator-white surface with solar absorptivity 0.11 and infrared emissivity 0.91. This temperature is well under 175C target we use for the limits of high-temperature silicon integrated circuits, including RAM and microcontrollers. We could further reduce this operating temperature to as low as 321K (48°C) with an advanced thermal coating, a temperature well within the operational limits of conventional electronics

Mercury↗