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Lukco, Dorothy

Publications and source records attributed to Lukco, Dorothy.

At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS2019

Characterization of Silicon Carbide Pressure Sensors at 800 °C

We have performed the initial characterization of single crystal 4H silicon carbide (4H-SiC) pressure sensors to determine the operational reliability over time at 800 °C. Important parameters such as the zero pressure offset, bridge resistance, and pressure sensitivity as they are affected by temperature were extracted. These parameters showed relative stability within the prescribed operational envelop of the sensor at 800 °C. Of significance is the increase in pressure sensitivity with increasing temperature beyond 400 °C, to the extent that the sensitivity at 800 °C was higher than the room temperature value. The implication of this result is that the sensor can be inserted further into the high temperature environment, thereby capturing the wider bandwidth of the pressure transients than currently possible.

Okojie, Robert S.↗
NASA NTRS2018

Sixty Earth-Days Test of a Prototype Pt/HTCC Alumina Package in Simulated Venus Environment

This paper presents experimental results of a prototype high temperature co-fired ceramic (HTCC) package with Au/Pt metallization in a three-phase harsh environment test that culminated with 60-day demonstration in simulated Venus surface environment of 465 degrees Centigrade with corrosive atmosphere at 90 bars pressure. The prototype package is based on a previously developed and reported HTCC package successfully tested with multiple analog and digital silicon carbide (SiC) high temperatures semiconductor integrated circuits (ICs) at NASA Glenn Research Center in 500 degrees Centigrade Earth air ambient for over ten thousand hours, and short-term tested at temperatures above 800 degrees Centigrade. The three-phase harsh environment test started with 48 hours in 465 degrees Centigrade Earth air, followed by 48 hours in 465 degrees Centigrade nitrogen at 90-bar pressure and 1400 hours in simulated Venus surface environment of 465 degrees Centigrade with corrosive atmosphere at 90 bars. Initial analytical results of the package materials and surfaces after exposure to the Venus environment are discussed to assess the stability of the packaging materials in the tested environments. The test in a simulated Venus environment was implemented in the NASA Glenn Extreme Environment Rig (GEER). The results of this study suggest that an effective encapsulation of areas of surface metallization and vicinities may help to improve electrical performance of a HTCC alumina packaging system in Venus environment.

Chen, Liang-Yu↗
NASA NTRS2018

Sixty Earth-Days Test of a Prototype Pt/HTCC Alumina Package in Simulated Venus Environment

This paper presents experimental results of a prototype high temperature co-fired ceramic (HTCC) package with Au/Pt metallization in a three-phase harsh environment test that culminated with 60-day demonstration in simulated Venus surface environment of 465 degC with corrosive atmosphere at 90 bar pressure. The prototype package is based on previously developed and reported HTCC package successfully tested with multiple analog and digital silicon carbide (SiC) high temperatures semiconductor integrated circuits (ICs) at NASA Glenn Research Center in 500 degC Earth air ambient for over ten thousands hours, and short-term tested at temperatures above 800 degC. The three-phase harsh environment test started with 48 hours in 465 degC Earth air, followed by 48 hours in 465 degC nitrogen at 90 bar pressure and 1400 hours in simulated Venus surface environment of 465 degC with corrosive atmosphere at 90 bar. Initial analytical results of the package materials and surfaces after exposure to Venus environment are discussed to assess the stability of the packaging materials in the tested environments. The test in simulated Venus environment was implemented in the NASA Glenn Extreme Environment Rig (GEER). The results of this study suggest that an effective encapsulation of areas of surface metallization and vicinities may help to improve electrical performance of a HTCC alumina packaging system in Venus environment.

Chen, Liangyu↗
NASA NTRS2018

Investigation of Alpha Silicon Carbide / Carbon Fiber Proposed (2H & 6H-SiC) / C

A commercially available alpha silicon carbide coated carbon 12k fiber tow was subjected to rigorous inspection and testing. The pyrolized polyacrylonitrile (PAN) fiber had gone through a conversion process that resulted in a thin layer of SiC forming on the exterior of the fiber. The fibers? surface was characterized by x-ray photoelectron spectroscopy (XPS), Auger electron spectroscopy (AES) and scanning electron microscopy (SEM). Powdered x-ray diffraction (XRD) examined the bulk material properties. Transmission electron microscopy (TEM) coupled with energy-dispersive X-ray spectroscopy (EDS) examined the crystallinity of the SiC. A number of pristine samples were used to determine elongation rate and tensile strength.

Trunek, Andrew↗
NASA NTRS2017

Prolonged 500 C Operation of 100+ Transistor Silicon Carbide Integrated Circuits

This report describes more than 5000 hours of successful 500 C operation of semiconductor integrated circuits (ICs) with more than 100 transistors. Multiple packaged chips with two different 4H-SiC junction field effect transistor (JFET) technology demonstrator circuits have surpassed thousands of hours of oven-testing at 500 C. After 100 hours of 500 C burn-in, the circuits (except for 2 failures) exhibit less than 10 change in output characteristics for the remainder of 500C testing. We also describe the observation of important differences in IC materials durability when subjected to the first nine constituents of Venus-surface atmosphere at 9.4 MPa and 460C in comparison to what is observed for Earth-atmosphere oven testing at 500 C.

Silicon Carbid↗
NASA NTRS2017

Prolonged 500 C Operation of 100+ Transistor Silicon Carbide Integrated Circuits

This report describes more than 5000 hours of successful 500 C operation of semiconductor integrated circuits (ICs) with more than 100 transistors. Multiple packaged chips with two different 4H-SiC junction field effect transistor (JFET) technology demonstrator circuits have surpassed thousands of hours of oven-testing at 500 C. After 100 hours of 500 C burn-in, the circuits (except for 2 failures) exhibit less than 10% change in output characteristics for the remainder of 500 C testing. We also describe the observation of important differences in IC materials durability when subjected to the first nine constituents of Venus-surface atmosphere at 9.4 MPa and 460 C in comparison to what is observed for Earth-atmosphere oven testing at 500 C.

Spry, David J.↗
NASA NTRS2017

Pt: Ti Diffusion Barrier, Interconnect, and Simultaneous Ohmic Contacts to n- and p-type 4H-SiC

We report the initial results of using co-sputtered Pt:Ti 80:20 at. % composition ratio metallization as a diffusion barrier against gold (Au) and oxygen (O), as an interconnect layer, as well as forming simultaneous ohmic contacts to n-and p-type 4H-SiC. Having a single conductor with such combined multi-functional attributes would appreciably reduce the fabrication costs, processing time and complexity that are inherent in the production of SiC based devices. Auger Electron Spectroscopy, Focused Ion Beam-assisted Field Emission Scanning Electron Microscopy and Energy Dispersive Spectroscopy analyses revealed no Au and O migration to the SiC contact surface and minimal diffusion through the Pt:Ti barrier layer after 15 minutes of exposure at 800 °C in atmosphere, thus offering potential long term stability of the ohmic contacts. Specific contact resistance values of 7 x 10(exp -5) and 7.4 x 10(exp -4) Ω-sq.cm were obtained on the n (N(sub d)=7 x 10(exp 18) per cu.cm and p (N(sub a)=2 x 10(exp 20) per cu. cm) -type 4H-SiC, respectively. The resistivity of 75 μΩ-cm was obtained for the Pt:Ti layer that was sandwiched between two SiO2 layers and annealed in pure O ambient up to 900 °C, which offers promise as a high temperature interconnect metallization.

Simultaneous Ohmic Contact↗
NASA NTRS2017

Chemical and Microstructural Changes in Metallic and Ceramic Materials Exposed to Venusian Surface Conditions

The chemical and microstructural behavior of steels (304, 310, 316, and 1018), nickel-based alloys (beta-NiAl, G30, and 625), gold, coatings (4YSZ, SilcoNert(TradeMark) 1040 (SilcoTek Co.), Dursan(TradeMark) (SilcoTek Co.), and porcelain), and bulk ceramics (alpha-Al2O3, fused quartz, beta-SiC, and alpha-Si3N4) were probed after exposure to supercritical fluid with temperature, pressure, and composition mimicking the Venus lower atmosphere. Exposures were carried out in the Glenn Extreme Environments Rig (GEER) chamber with the Venusian gas mixture (96.5% CO2, 3.5% N2, 30 ppm H2O, 150 ppm SO2, 28 ppm CO, 15 ppm OCS, 3 ppm H2S, 0.5 ppm HCl, and 5 ppb HF) at 92 bar (1330 psi) and 467 C (873 F) for durations of 10 and 42 days. An additional 21-day exposure was done to stainless steel uncoated and coated with SilcoNert(TradeMark) and Dursan(TradeMark). Samples were characterized before and after the experiment by gravimetric analysis, X-ray diffraction, X-ray photoelectron and Auger electron spectroscopies, and cross section electron microscopy analysis. All steels exposed for 10 and 42 days formed double-layered scales consisting mainly of metal (Cr, Fe, Ni) oxides and sulfides showing different chemistry, microstructure, and crystalline phases. The alloys G30 and 625 formed double-layered scales consisting mainly of nickel sulfides. After 10 days, the beta-NiAl exhibited no detectable scale, suggesting only a very thin film was formed. The 304 and 316 stainless steels coated with 4YSZ that were exposed for 10 and 42 days exhibited no significant oxidation. Steel 1018 coated with 4YSZ exhibited a corrosion scale of iron and/or chromium oxide formed at the base of the alloy. The 304 steel coated with porcelain did not exhibit corrosion, although the coating exhibited recession. SilcoNert(TradeMark) exposed for 10 and 42 days exhibited recession, although no oxidation was found to occur at the base of the alloy. Stainless steel 316 coated with Dursan(TradeMark)  exhibited corrosion at the base of the alloy. All ceramics tested showed no clear evidence of reaction. The weight-gain-per-area performance of the materials exposed in the GEER for 10 and 42 days are reported from the lowest to the highest weight gain per area as follows: gold did not exhibit any weight change; nickel-based alloys: beta- NiAl < G30 < 625; steels: 304 < 310 < 316 < 1018; ceramics: considering the experimental uncertainties, no weight change was observed for all ceramics of this work (alpha-Al2O3, Si3N4, SiC, and amorphous SiO2).

Costa, Gustavo C. C.↗
NASA NTRS2017

High Temperature Characteristics of Pt/TaSi2/Pt/W and Pt/Ti/W Diffusion Barrier Systems for Ohmic Contacts to 4H-SiC

The degradation of ohmic contacts to 4H-SiC pressure sensors over time at high temperature is primarily due to two failure mechanisms: migrating bond pad Au and atmospheric O toward the ohmic contact SiC interface and the inter-metallic mixing between diffusion barrier systems (DBS) and the underlying ohmic contact metallization. We investigated the effectiveness of Pt/TaSi2/Pt/W (DBS-A) and Pt/Ti/W (DBS-B) in preventing Au and O diffusion through the underlying binary Ti/W or alloyed W50:Ni50 ohmic contacts to 4H-SiC and the DBS ohmic contact intermixing at temperature up to 700 C.

Platinum↗
NASA NTRS2016

Experimentally Observed Electrical Durability of 4H-SiC JFET ICs Operating from 500 C to 700 C

Prolonged 500 degrees Celsius to 700 degrees Celsius electrical testing data from 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) are combined with post-testing microscopic studies in order to gain more comprehensive understanding of the durability limits of the present version of NASA Glenn's extreme temperature microelectronics technology. The results of this study support the hypothesis that T ≥ 500 degrees Celsius durability-limiting IC failure initiates with thermal-stress-related crack formation where dielectric passivation layers overcoat micron-scale vertical features including patterned metal traces.

high temperature↗
NASA NTRS2016

Processing and Characterization of Thousand-Hour 500 C Durable 4H-SiC JFET Integrated Circuits

This work reports fabrication and testing of integrated circuits (ICs) with two levels of interconnect that consistently achieve greater than 1000 hours of stable electrical operation at 500 C in air ambient. These ICs are based on 4H-SiC junction field effect transistor (JFET) technology that integrates hafnium ohmic contacts with TaSi2 interconnects and SiO2 and Si3N4 dielectric layers over approximately 1-micrometer scale vertical topology. Following initial burn-in, important circuit parameters remain stable for more than 1000 hours of 500 C operational testing. These results advance the technology foundation for realizing long-term durable 500 C ICs with increased functional capability for sensing and control combustion engine, planetary, deep-well drilling, and other harsh-environment applications.

Microelectronics↗
NASA NTRS2016

Experimental Durability Testing of 4H SiC JFET Integrated Circuit Technology at 727 Degrees Centigrade

We have reported SiC integrated circuits (ICs) with two levels of metal interconnect that have demonstrated prolonged operation for thousands of hours at their intended peak ambient operational temperature of 500 degrees Centigrade. However, it is recognized that testing of semiconductor microelectronics at temperatures above their designed operating envelope is vital to qualification. Towards this end, we previously reported operation of a 4H-SiC JFET IC ring oscillator on an initial fast thermal ramp test through 727 degrees Centigrade. However, this thermal ramp was not ended until a peak temperature of 880 degrees Centigrade (well beyond failure) was attained. Further experiments are necessary to better understand failure mechanisms and upper temperature limit of this extreme-temperature capable 4H-SiC IC technology.Here we report on additional experimental testing of custom-packaged 4H-SiC JFET IC devices at temperatures above 500 degrees Centigrade. In one test, the temperature was ramped and then held at 727 degrees Centigrade, and the devices were periodically measured until electrical failure was observed. A 4H-SiC JFET on this chip electrically functioned with little change for around 25 hours at 727 degrees Centigrade before rapid increases in device resistance caused failure. In a second test, devices from our next generation 4H-SiC JFET ICs were ramped up and then held at 700 degrees Centigrade (which is below the maximum deposition temperature of the dielectrics). Three ring oscillators functioned for 8 hours at this temperature before degradation. In a third experiment, an alternative die attach of gold paste and package lid was used, and logic circuit operation was demonstrated for 143.5 hours at 700 degrees Centigrade.

Silicon Carbide↗
NASA NTRS2016

Experimental Durability Testing of 4H SiC JFET Integrated Circuit Technology at 727 C

We have reported SiC integrated circuits (IC's) with two levels of metal interconnect that have demonstrated prolonged operation for thousands of hours at their intended peak ambient operational temperature of 500 C [1, 2]. However, it is recognized that testing of semiconductor microelectronics at temperatures above their designed operating envelope is vital to qualification. Towards this end, we previously reported operation of a 4H-SiC JFET IC ring oscillator on an initial fast thermal ramp test through 727 C [3]. However, this thermal ramp was not ended until a peak temperature of 880 C (well beyond failure) was attained. Further experiments are necessary to better understand failure mechanisms and upper temperature limit of this extreme-temperature capable 4H-SiC IC technology. Here we report on additional experimental testing of custom-packaged 4H-SiC JFET IC devices at temperatures above 500 C. In one test, the temperature was ramped and then held at 727 C, and the devices were periodically measured until electrical failure was observed. A 4H-SiC JFET on this chip electrically functioned with little change for around 25 hours at 727 C before rapid increases in device resistance caused failure. In a second test, devices from our next generation 4H-SiC JFET ICs were ramped up and then held at 700 C (which is below the maximum deposition temperature of the dielectrics). Three ring oscillators functioned for 8 hours at this temperature before degradation. In a third experiment, an alternative die attach of gold paste and package lid was used, and logic circuit operation was demonstrated for 143.5 hours at 700 C.

JFET↗
NASA NTRS2015

Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype ICs with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3-and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient.

Silicon Carbide↗
NASA NTRS2015

Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated With Two Levels of Metal Interconnect

The fabrication and prolonged 500 C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 3000 hours at 500 C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 C operating time. Evidence is presented for four distinct issues that significantly impacted 500 C IC operational yield and lifetime for this wafer.

JFET↗
NASA NTRS2015

Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype IC's with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3- and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient. Improved reproducibility remains to be accomplished.

JFET↗
NASA NTRS2015

Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated with Two Levels of Metal Interconnect

The fabrication and prolonged 500 C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 1000 hours at 500 C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 C operating time. Evidence is presented for four distinct issues that significantly impacted 500 C IC operational yield and lifetime for this wafer.

Microelectronics↗