Engineering topics

Long, Stephen I.

Publications and source records attributed to Long, Stephen I..

6 records

NASA NTRS1992

A 600-MHz median-type digital filter on GaAs

A single-chip GaAs implementation of an FIR-median hybrid filter is presented. The very high-speed digital filter combines linear averaging structures to a median selector. The filter operates on 5-b samples with ECL-compatible I/O interfaces. The 1500-transistor LSI device with 3.6-sq mm chip size was processed with a 1.0-micron GaAs depletion-mode (D-mode) MESFET process. The filter demonstrates 600-MHz sample rate when operated in test mode utilizing special built-in feedback.

Vainjo, Olli↗

NASA NTRS1990

Simplified calculation of wave-coupling between lines in high-speed integrated circuits

The construction of time-domain solutions by the superposition of modes is explained for the general case, which may not have any symmetry in the lines or terminations. This simplified method requires that the logic-gate terminal impedances be approximated by linear effective resistances that can be adequately determined by SPICE analysis of the actual logic gates. Several examples of results of crosstalk calculations made by the simplified method are presented and compared with corresponding results obtained using the SPICE transmission-line methods of Tripathi and Rettig (1985) along with full SPICE models of the logic gates. The simplified approach is shown to give satisfactory agreement for most purposes.

Matthaei, George L.↗

NASA NTRS1990

Gallium Arsenide Domino Circuit

Advantages include reduced power and high speed. Experimental gallium arsenide field-effect-transistor (FET) domino circuit replicated in large numbers for use in dynamic-logic systems. Name of circuit denotes mode of operation, which logic signals propagate from each stage to next when successive stages operated at slightly staggered clock cycles, in manner reminiscent of dominoes falling in a row. Building block of domino circuit includes input, inverter, and level-shifting substages. Combinational logic executed in input substage. During low half of clock cycle, result of logic operation transmitted to following stage.

Yang, Long↗

NASA NTRS1990

High-speed dynamic domino circuit implemented with gaas mesfets

A dynamic logic circuit (AND or OR) utilizes one depletion-mode metal-semiconductor FET for precharging an internal node A, and a plurality of the same type of FETs in series, or a FET in parallel with one or more of the series connected FETs for implementing the logic function. A pair of FETs are connected to provide an output inverter with two series diodes for level shift. A coupling capacitor may be employed with a further FET to provide level shifting required between the inverter and the logic circuit output terminal. These circuits may be cascaded to form a domino chain.

Yang, Long↗

NASA NTRS1988

Noise-margin limitations on gallium-arsenide VLSI

Two factors which limit the complexity of GaAs MESFET VLSI circuits are considered. Power dissipation sets an upper complexity limit for a given logic circuit implementation and thermal design. Uniformity of device characteristics and the circuit configuration determines the electrical functional yield. Projection of VLSI complexity based on these factors indicates that logic chips of 15,000 gates are feasible with the most promising static circuits if a maximum power dissipation of 5 W per chip is assumed. While lower power per gate and therefore more gates per chip can be obtained by using a popular E/D FET circuit, yields are shown to be small when practical device parameter tolerances are applied. Further improvements in materials, devices, and circuits wil be needed to extend circuit complexity to the range currently dominated by silicon.

Long, Stephen I.↗

NASA NTRS1987

System architecture of a gallium arsenide one-gigahertz digital IC tester

The design for a 1-GHz digital integrated circuit tester for the evaluation of custom GaAs chips and subsystems is discussed. Technology-related problems affecting the design of a GaAs computer are discussed, with emphasis on the problems introduced by long printed-circuit-board interconnect. High-speed interface modules provide a link between the low-speed microprocessor and the chip under test. Memory-multiplexer and memory-shift register architectures for the storage of test vectors are described in addition to an architecture for local data storage consisting of a long chain of GaAs shift registers. The tester is constructed around a VME system card cage and backplane, and very little high-speed interconnect exists between boards. The tester has a three part self-test consisting of a CPU board confidence test, a main memory confidence test, and a high-speed interface module functional test.

Fouts, Douglas J.↗