Engineering topics

Liu, K.

Publications and source records attributed to Liu, K..

44 records · Page 3

NASA NTRS1991

Identification and control of NASA's ACES structures

Results are presented of identification and control experiments on NASA's ACES structure at the Marshall Space Flight Center. The models used for controller design were obtained from identification experiments employing the algorithm Q-Markov cover. The OVC algorithm used for control design produces a controller minimizing the control energy of the closed-loop system, subject to inequality constraints on each of the output variances. The identified model matches the experimental data for the ACES structure reasonably well. The line of sight pointing errors of the structure are substantially reduced by the controllers.

Liu, K.↗

NASA NTRS1990

A high speed CCSDS encoder for space applications

This paper reports a VLSI implementation of the CCSDS standard Reed Solomon encoder circuit for the Space Station. The 1.0 micron double metal CMOS chip is 5.9 mm by 3.6 mm, contains 48,000 transistors, operates at a sustained data rate of 320 Mbits/s, and executes 2,560 Mops. The chip features a pin selectable interleave depth of 1 to 8. Block lengths of up to 255 bytes, as well as shortened codes, are supported. The control circuitry uses register cells which are immune to Single Event Upset. In addition, the CMOS process used is reported to be tolerant of over 1 Mrad total dose radiation.

Whitaker, S.↗

NASA NTRS1990

SEU hardening of CMOS memory circuit

This paper reports a design technique to harden CMOS memory circuits against Single Event Upset (SEU) in the space environment. A RAM cell and Flip Flop design are presented to demonstrate the method. The Flip Flop was used in the control circuitry for a Reed Solomon encoder designed for the Space Station.

Whitaker, S.↗

NASA NTRS1990

CCSDS Reed Solomon VLSI chip set

A highly efficient error correcting code has been selected by NASA as a CCSDS standard: the 16 symbol error correcting Reed Solomon code. A VLSI implementation of this decoder is described in this paper. A total of 4 full custom VLSI chips are needed that correct data in real time at an sustained rate of up to 80 Mbits/second.

Cameron, K.↗

NASA NTRS1990

PLA realizations for VLSI state machines

A major problem associated with state assignment procedures for VLSI controllers is obtaining an assignment that produces minimal or near minimal logic. The key item in Programmable Logic Array (PLA) area minimization is the number of unique product terms required by the design equations. This paper presents a state assignment algorithm for minimizing the number of product terms required to implement a finite state machine using a PLA. Partition algebra with predecessor state information is used to derive a near optimal state assignment. A maximum bound on the number of product terms required can be obtained by inspecting the predecessor state information. The state assignment algorithm presented is much simpler than existing procedures and leads to the same number of product terms or less. An area-efficient PLA structure implemented in a 1.0 micron CMOS process is presented along with a summary of the performance for a controller implemented using this design procedure.

Gopalakrishnan, S.↗

NASA NTRS1990

Optimal controllers for finite wordlength implementation

There exist realizations of a given controller transfer function yielding arbitrarily large effects from computational errors. Since, in general, there is no upper bound, it is important to have a systematic way of reducing these effects. Optimum controller designs are developed which take into account the digital round-off errors in the controller implementation and in the A/D and D/A converters. These results provide a natural extension to the LQG (linear quadratic Gaussian) theory since they reduce to the standard LQG controller when infinite-precision computation is used, but for finite precision the separation principle does not hold.

Liu, K.↗

NASA NTRS1990

An iterative algorithm combining model reduction and control design

A design strategy which integrates model reduction by modal cost analysis and a multiobjective controller design is proposed. The necessary modeling and control algorithms are easily programmed in Matlab standard software. Hence, this method is very practical for controller design for large space structures. The design algorithm also solves the very important problem of tuning multiple loop controllers (multi-input, multi-output, or MIMO). Instead of the single gain change that is used in standard root locus and gain and phase margin theories, this method tunes multiple loop controllers from low to high gain in a systematic way in the design procedure. This design strategy is applied to NASA's Mini-Mast system.

Hsieh, C.↗

NASA NTRS1984

Software conversion history of the Flight Dynamics System (FDS)

This report summarizes the overall history of the Flight Dynamics System (FDS) applications software conversion project. It describes the background and nature of the project; traces the actual course of conversion; assesses the process, product, and personnel involved; and offers suggestions for future projects. It also contains lists of pertinent reference material and examples of supporting data.

Liu, K.↗