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Liu, J. K.

Publications and source records attributed to Liu, J. K..

99 records · Page 6
All sourcesNASA NTRSDOE OSTI
NASA NTRS1988

Studies of molecular-beam epitaxy growth of GaAs on porous Si substrates

GaAs has been grown on porous Si directly and on Si buffer layer-porous Si substrates by molecular-beam epitaxy. In the case of GaAs growth on porous Si, transmission electron microscopy (TEM) reveals that the dominant defects in GaAs layers grown on porous Si are microtwins and stacking faults, which originate from the GaAs/porous Si interface. GaAs is found to penetrate into the porous Si layers. By using a thin Si buffer layer (50 nm), GaAs penetration diminishes and the density of microtwins and stacking faults is largely reduced and localized at the GaAs/Si buffer interface. However, there is a high density of threading dislocations remaining. Both Si (100) aligned and four degree tilted substrates have been examined in this study. TEM results show no observable effect of the tilted substrates on the quality of the GaAs epitaxial layer.

Mii, Y. J.↗
NASA NTRS1987

Growth and characterization of molecular beam epitaxial GaAs layers on porous silicon

GaAs layers have been grown on porous silicon (PS) substrates with good crystallinity by molecular beam epitaxy. In spite of the surface irregularity of PS substrates, no surface morphology deterioration was observed on epitaxial GaAs overlayers. A 10-percent Rutherford backscattering spectroscopy minimum channeling yield for GaAs-on-PS layers as compared to 16 percent for GaAs-on-Si layers grown under the same condition indicates a possible improvement of crystallinity when GaAs is grown on PS. Transmission electron microscopy reveals that the dominant defects in the GaAs-on-PS layers are microtwins and stacking faults, which originate from the GaAs/PS interface. GaAs is found to penetrate into the PS layers. n-type GaAs/p-type PS heterojunction diodes were fabricated with good rectifying characteristics.

Lin, T. L.↗
NASA NTRS1985

Activated Internal Gettering

Lifetimes of minority carriers in silicon webs improved by annealing. Heat treatment of silicon web ribbons considerably improves efficiency of solar cells.

Liu, J. K.↗
NASA NTRS1983

Method of increasing minority carrier lifetime in silicon web or the like

A silicon dendrite is grown as a ribbon forming two silicon crystal layers which are separated by an interface layer which contains a large number of defects. Significant increase of minority carrier lifetime with homogeneous distribution at the outer surfaces of the two silicon crystal layers is achieved by processing the web in an atmosphere of a selected gas, e.g., oxygen, nitrogen or an inert gas, for about 30 minutes to several hours at a temperature preferably on the order of 900 to 1200 C.

Liu, J. K.↗
NASA NTRS1981

Current status of solar cell performance of unconventional silicon sheets

It is pointed out that activities in recent years directed towards reduction in the cost of silicon solar cells for terrestrial photovoltaic applications have resulted in impressive advancements in the area of silicon sheet formation from melt. The techniques used in the process of sheet formation can be divided into two general categories. All approaches in one category require subsequent ingot wavering. The various procedures of the second category produce silicon in sheet form. The performance of baseline solar cells is discussed. The baseline process included identification marking, slicing to size, and surface treatment (etch-polishing) when needed. Attention is also given to the performance of cells with process variations, and the effects of sheet quality on performance and processing.

Yoo, H. I.↗
NASA NTRS1981

Economics of ingot slicing with an internal diameter saw for low-cost solar cells

Slicing of silicon ingots using diamond impregnated internal diameter blade saws has been a standard technology of the semiconductor industry. This paper describes work on improvements to this technology for 10 cm diameter ingot slicing. Ingot rotation, dynamic blade edge control with feedback, mechanized blade dressing and development of thinner blades are the approaches tried. A comparison of the results for wafering with and without ingot rotation is also made. A sensitivity analysis of the major cost elements in wafering is performed for 10 cm diameter ingot and extended to the 15 cm diameter ingot case. Various parameter values such as machine cost, feed rate and consumable materials cost are identified both for single and multiple ingot slicing.

Daud, T.↗
NASA NTRS1979

Some characteristics of low-cost silicon sheet

The paper discusses structural defects in low-cost silicon sheets and their effect on the electronic properties related to solar cell performance. Experimental data are presented on the influence of grain boundaries on minority carrier diffusion length, impurity defect interaction, and variable surface recombination velocity. An analytical model of the effect of grain boundaries on solar cell performance is constructed based on these results.

Koliwad, K. M.↗
NASA NTRS1978

Effect of multiblade slurry saw induced damage on silicon solar cells

A correlation between the optimum etch loss and the depth of damage is established using wafers produced by the Multiblade Slurry (MBS) and the Internal Diameter (ID) saws. The observations are based on the measurement of the performance of solar cells fabricated on these wafers. Sample preparation and test results are described and the following conclusions are made: (1) the amount of silicon removal necessary for optimum solar cell performance coincides with the depth of saw-induced damage; (2) optimization of cell performance is not affected by the method of silicon removal; (3) sawing conditions should be optimized to minimize the extent of saw-induced damage; (4) the MBS saw is found to induce damage to a lesser extent; (5) since the extent of damage in MBS-sawn wafers is in the limit of etch loss required in texture etching, it is possible to achieve optimum improvement in cell performance by merely texture etching the surface of as-sawn wafers.

Daud, T.↗