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Lin, H. C.

Publications and source records attributed to Lin, H. C..

32 records · Page 2
All sourcesNASA NTRSDOE OSTI
NASA NTRS1976

Modeling of short channel MOS transistors

Higher frequency response in MOS technology can be obtained by shortening the channel length. One approach for doing this involves an employment of higher resolution lithography technology. A second approach makes use of a double-diffused MOS transistor (DMOS). It is pointed out that the ordinary method of modeling the transistors used in both approaches is not accurate. An investigation is conducted of the questions which have to be considered for DMOS modeling. The modeling of a short channel MOS transistor is discussed, taking into account the derivation of the threshold voltage equation. Excellent agreement between theoretical and experimental data shows the accuracy of the described modeling approach.

Lin, H. C.↗
NASA NTRS1975

Noise performance of very large antenna arrays

The maximum size and resolution of receiving antenna arrays is found to be limited by signal-to-noise ratio considerations. For square arrays containing no active elements, a practical limit at 30 GHz appears to be on the order of 10 meters for communications and one to two meters for radiometry. These limitations can be overcome by use of active devices at various levels of the array organization. The nature of the resulting tradeoffs is indicated. Explicit formulas are developed for both passive and active arrays, and sample computations and the computer programs are given.

Lin, H. C.↗
NASA NTRS1975

An optimized output stage for MOS integrated circuits

An output device for optimizing propagation delay and minimizing chip area is described. An optimum means of tapering the output stages to minimize propagation delay is determined. The minimum delay is a function of the capacitive load to node ratio, the number of output stages, and the interstage propagation delay. The effects on area are also presented. A figure of merit which is a function of area and propagation time is defined which is of use in designing output stages. An optimum exists which can be considered the best compromise between further decreasing propagation delay and increasing chip area. Data are also presented which allow a designer to determine the minimum chip area once the capacitive load and the maximum allowable delay are known.

Lin, H. C.↗
NASA NTRS1974

Experimental investigation of a shielded complementary Metal-Oxide Semiconductor (MOS) structure

A shielded integrated complimentary MOS transistor structure is described which is used to prevent field inversion in the region not occupied by the gates and which permits the use of a thinner field oxide, reduces the chip area, and has provision for simplified multilayer connections. The structure is used in the design of a static shift register and results in a 20% reduction in area.

Lin, H. C.↗
NASA NTRS1972

Shielded silicon gate complementary MOS integrated circuit.

An electrostatic shield for complementary MOS integrated circuits was developed to minimize the adverse effects of stray electric fields created by the potentials in the metal interconnections. The process is compatible with silicon gate technology. N-doped polycrystalline silicon was used for all the gates and the shield. The effectiveness of the shield was demonstrated by constructing a special field plate over certain transistors. The threshold voltages obtained on an oriented silicon substrate ranged from 1.5 to 3 V for either channel. Integrated inverters performed satisfactorily from 3 to 15 V, limited at the low end by the threshold voltages and at the high end by the drain breakdown voltage of the n-channel transistors. The stability of the new structure with an n-doped silicon gate as measured by the shift in C-V curve under 200 C plus or minus 20 V temperature-bias conditions was better than conventional aluminum gate or p-doped silicon gate devices, presumably due to the doping of gate oxide with phosphorous.

Lin, H. C.↗
NASA NTRS1970

Low power NAND gate

Complementary p-n-p transistor, used as the load resistor in an integrated circuit, reduces the switching time and the steady state dc current, and allows for a lower supply voltage. Current limiting is achieved by a novel unity-gain transistor.

Lin, H. C.↗
NASA NTRS1969

Integrated circuit with multiple collector current source

Integrated circuit with multiple collector current source achieves the equivalent of a large number of resistors in a small area. Functional equivalents of a transistor reduce the size requirement for low power integrated circuits, providing an efficient alternative to the conventional diffused resistor process in integrated circuit fabrication.

Hellstrom, M. J.↗