Lanni, Francesco | Engineering Papers

DOE OSTI2024

High-data throughput reconfigurable computing platform

A reconfigurable computing platform includes a reconfigurable computing device, electro-optical transceiver, and first voltage converter disposed on a multilayer board. The electro-optical transceiver converts an optical signal at least one of to and from an electrical signal, and the electrical signal is operatively coupled to the reconfigurable computing device. The electro-optical transceiver is disposed in proximity to the reconfigurable computing device, and the first voltage converter is operatively coupled to a common voltage distributed around a periphery of the multilayer board. The first voltage converter converts the common voltage to a first operating voltage, and the first voltage converter is disposed in proximity to the reconfigurable computing device. The first operating voltage is provided to the reconfigurable computing device as a first power source. A reconfigurable computing system includes a plurality of reconfigurable computing platforms operatively coupled together using an optical signal. A corresponding method of providing a reconfigurable computing platform is also disclosed.

Tang, Shaochun↗

DOE OSTI2023

High-bandwidth reconfigurable data acquisition card

A reconfigurable data acquisition card including at least one field programmable gate array (FPGA) and a configurable bus switch coupled with the FPGA. The bus switch forms at least first and second ports used by the FPGA, the bus switch being adaptable for insertion into a connection having a number of lanes at least equal to a combined number of lanes in the first and second ports. The data acquisition card further includes multiple optical transmitters and optical receivers. Each optical transmitter and optical receiver is coupled with a corresponding transceiver in the FPGA via at least one optical fiber having multiple communication links. Timing circuitry in the data acquisition card is coupled with clock generation and distribution circuitry in the FPGA and is configured to distribute clock and timing signals to detector front-ends with fixed latency and to synchronize input/output links with a system clock generated by the FPGA.

Chen, Kai↗