Engineering topics

Lanni, Francesco

Publications and source records attributed to Lanni, Francesco.

9 records

DOE OSTI2024

High-data throughput reconfigurable computing platform

A reconfigurable computing platform includes a reconfigurable computing device, electro-optical transceiver, and first voltage converter disposed on a multilayer board. The electro-optical transceiver converts an optical signal at least one of to and from an electrical signal, and the electrical signal is operatively coupled to the reconfigurable computing device. The electro-optical transceiver is disposed in proximity to the reconfigurable computing device, and the first voltage converter is operatively coupled to a common voltage distributed around a periphery of the multilayer board. The first voltage converter converts the common voltage to a first operating voltage, and the first voltage converter is disposed in proximity to the reconfigurable computing device. The first operating voltage is provided to the reconfigurable computing device as a first power source. A reconfigurable computing system includes a plurality of reconfigurable computing platforms operatively coupled together using an optical signal. A corresponding method of providing a reconfigurable computing platform is also disclosed.

Tang, Shaochun↗

DOE OSTI2023

High-bandwidth reconfigurable data acquisition card

A reconfigurable data acquisition card including at least one field programmable gate array (FPGA) and a configurable bus switch coupled with the FPGA. The bus switch forms at least first and second ports used by the FPGA, the bus switch being adaptable for insertion into a connection having a number of lanes at least equal to a combined number of lanes in the first and second ports. The data acquisition card further includes multiple optical transmitters and optical receivers. Each optical transmitter and optical receiver is coupled with a corresponding transceiver in the FPGA via at least one optical fiber having multiple communication links. Timing circuitry in the data acquisition card is coupled with clock generation and distribution circuitry in the FPGA and is configured to distribute clock and timing signals to detector front-ends with fixed latency and to synchronize input/output links with a system clock generated by the FPGA.

Chen, Kai↗

DOE OSTI2020

A Generic High Bandwidth Data Acquisition Card for Physics Experiments

In high energy physics and nuclear physics experiments particularly the ones based on particle accelerator, the data rate from the detector is usually in the order of Terabytes per second. This high throughput data from detector front-end electronics need to be transmitted to the back-end computing farm for high level event selection and building. A Data Acquisition (DAQ) system with features of high-density, scalable, easily upgradeable is crucial to simplify the readout architecture of whole experiment. This paper will introduce the design of a generic high bandwidth PCIe card which can be used as the important input output card in a scalable DAQ system. It can factorize front-end electronics from data handling, and reduce amount of custom hardware in favor of scalable detectorindependent commercial hardware and software. Besides the 48 channels of bidirectional high speed fiber optical links with frontends, it also supports to synchronize with the experiment timing system, and to fanout the clock and trigger information with a fixed latency to the front-end electronics.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗

DOE OSTI2019

Basic Research Needs for High Energy Physics Detector Research & Development: Report of the Office of Science Workshop on Basic Research Needs for HEP Detector Research and Development: December 11-14, 2019

Transformative discovery in science is driven by innovation in technology. Our boldest undertakings in particle physics have at their foundation precision instrumentation. To reveal the profound connections underlying everything we see from the smallest scales to the largest distances in the Universe, to understand its fundamental constituents, and to reveal what is still unknown, we must invent, develop, and deploy advanced instrumentation. Investments in High Energy Physics (HEP) enabled by instrumentation have been richly rewarded with discoveries of the tiny masses of the neutrinos, the origin of mass itself: the enigmatic Higgs boson, and the surprising accelerating expansion of the Universe. What we have learned is remarkable, unexpected, exciting and mysterious; raising many new questions waiting to be answered. The quest to answer them drives innovation that improves the nation's health, wealth, and security, inspiring the public and drawing young people to science. Excellence and innovation come most effectively from diverse teams of people. Success, therefore, depends critically on attracting, engaging, and supporting a diverse cadre of young people to the field, and ensuring an inclusive environment at all levels. The program laid out in the 2014 Particle Physics Projects Prioritization Panel (P5) report "Building for Discovery - A Strategic Plan for U.S. Particle Physics in a Global Context" guides current and near future experiments to exploit these and other discoveries, and the instrumentation innovation they require, to push the frontiers of science into new territory. To explore this territory HEP will soon embark on planning the next generation of experiments. Realizing these experiments will require giant leaps in capabilities beyond the instrumentation of today. Accordingly, now is a pivotal moment to invest in the accelerated development of cost-effective instrumentation with greatly improved sensitivity and performance that will make measurable the unmeasurable, enabling a tool-driven revolution to open the door to future discoveries. Historic scientific opportunities await us, enabled by executing the instrumentation research plan outlined here.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2019

Design and Evaluation of the LAr Trigger Digitizer Board in the ATLAS Phase-I Upgrade

The Phase-I upgrade of the trigger readout electronics for the ATLAS Liquid Argon (LAr) calorimeters will be installed during the second long shutdown of the Large Hadron Collider (LHC) in 2019-2020 which will enable enhanced instantaneous luminosities during LHC Run 3 from 2021 through 2023. In this trigger upgrade, so-called supercells are introduced to provide higher granularity, higher resolution and longitudinal shower shape information from the LAr calorimeters to the Level-1 trigger processors. A new LAr Trigger Digitizer Board (LTDB) will process and digitize up to 320 channels of supercell signals, and transmit them via 40 fiber optical links to the back end where the data are further processed and transmitted to the trigger processors. Five pairs of bidirectional GBT links are used for slow control and monitoring between LTDB and the Front-End LInk eXchange (FELIX) in the ATLAS Trigger and Data Acquisition (TDAQ) system. Here, the LTDB also outputs 64 summed analog legacy signals to the current Tower Builder Board via a new baseplane. A test system for the production of 124 LTDBs has been developed, supporting configuration and calibration of all ASICs

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗

DOE OSTI2019

Development and data path integration test of the global Feature EXtractor for the ATLAS Level-1 calorimeter trigger system Phase-I upgrade

The global Feature Extractor (gFEX) is a component of the Phase-I upgrade of the Level-1 Calorimeter (L1Calo) trigger system for the ATLAS experiment at the Large Hadron Collider (LHC) at CERN. The gFEX is used to identify patterns of energy associated with the hadronic decays of high momentum Higgs, W and Z bosons, top quarks, and exotic particles in real time at the 40 MHz LHC bunch crossing rate. Three prototypes were implemented and tested from 2014 to 2017. With the lessons learned from the prototypes, the final gFEX production board has been implemented at the end of 2017. The gFEX receives up to 300 fiber optical links from the calorimeter and transmits trigger data on 96 links to the ATLAS Level-1 Topological [1] (L1Topo) trigger at a rate of up to 12.8 Gb/s. There are also 24 electrical links on board for communication between two FPGAs running at speeds of up to 25.6 Gb/s. Here, the hardware functionality and performance of the production board have been evaluated. A data path integration test between the Liquid Argon Digital Processing Blade (LDPB) [2] and the Front End LInk eXchange (FELIX) [3] was performed successfully at CERN in 2018.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗

DOE OSTI2019

Development of a technology for the fabrication of Low-Gain Avalanche Diodes at BNL

Low-Gain Avalanche Detectors are gathering interest in the High-Energy Physics community thanks to their fast-timing and radiation-hardness properties. One example of this includes plans to exploit timing detectors for the upgrades of the ATLAS and CMS detectors at the High Luminosity LHC. This new technology has also raised interest for its possible application for photon detection in medical physics, imaging and photon science. The main characteristic of this type of device is a thin and highly-doped layer that provides internal and moderate gain, in the order of 10–20, that enhances the signal amplitude. Furthermore the thin substrate, of only few tens of microns, allows for fast carrier collection. This paper offers here details on the fabrication technology, specifically developed at Brookhaven National Laboratory for the detection of minimum ionizing particles. The static electrical characterization and the gain measurements on prototypes will be also reported.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2019

Performance of CMOS pixel sensor prototypes in ams H35 and aH18 technology for the ATLAS ITk upgrade

Pixel sensors based on commercial high-voltage CMOS processes are an exciting technology that is considered as an option for the outer layer of the ATLAS inner tracker upgrade at the High Luminosity LHC. Here, charged particles are detected using deep n-wells as sensor diodes with the depleted region extending into the silicon bulk. Both analog and digital readout electronics can be added to achieve different levels of integration up to a fully monolithic sensor. Small scale prototypes using the ams CMOS technology have previously demonstrated that it can achieve the required radiation tolerance of 10(15) n(eq)/cm(2) and detection efficiencies above 99.5%. Recently, large area prototypes, comparable in size to a full sensor, have been produced that include most features required towards a final design: the H35demo prototype produced in ams H35 technology that supports both external and integrated readout and the monolithic ATLASPix1 pre-production design produced in ams aH18 technology. Both chips are based on large fill-factor pixel designs, but differ in readout structure. Performance results for H35DEMO with capacitively-coupled external readout and first results for the monolithic ATLASPix1 are shown.

ATLAS ITk upgrade↗

DOE OSTI2017

Development of an ADC radiation tolerance characterization system for the upgrade of the ATLAS LAr calorimeter

ATLAS LAr calorimeter will undergo its Phase-I upgrade during the long shutdown (LS2) in 2018, and a new LAr Trigger Digitizer Board (LTDB) will be designed and installed. Several commercial-off-the-shelf (COTS) multi-channel high-speed ADCs have been selected as possible backups of the radiation tolerant ADC ASICs for the LTDB. Here, to evaluate the radiation tolerance of these backup commercial ADCs, we developed an ADC radiation tolerance characterization system, which includes the ADC boards, data acquisition (DAQ) board, signal generator, external power supplies and a host computer. The ADC board is custom designed for different ADCs, with ADC drivers and clock distribution circuits integrated on board. The Xilinx ZC706 FPGA development board is used as a DAQ board. The data from the ADC are routed to the FPGA through the FMC (FPGA Mezzanine Card) connector, de-serialized and monitored by the FPGA, and then transmitted to the host computer through the Gigabit Ethernet. A software program has been developed with Python, and all the commands are sent to the DAQ board through Gigabit Ethernet by this program. Two ADC boards have been designed for the ADC, ADS52J90 from Texas Instruments and AD9249 from Analog Devices respectively. TID tests for both ADCs have been performed at BNL, and an SEE test for the ADS52J90 has been performed at Massachusetts General Hospital (MGH). Test results have been analyzed and presented. The test results demonstrate that this test system is very versatile, and works well for the radiation tolerance characterization of commercial multi-channel high-speed ADCs for the upgrade of the ATLAS LAr calorimeter. It is applicable to other collider physics experiments where radiation tolerance is required as well.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗