Engineering topics

Jordan, Matthew B.

Publications and source records attributed to Jordan, Matthew B..

4 records

DOE OSTI2023

Antenna With Embedded Die in Glass Interposer for 6G Wireless Applications

This article presents the antenna-integrated glass interposer for D-band 6G wireless applications using dieembedding technology. Here, we implement the die-embedded package on glass substrates and characterize the electrical performance in the D-band. The electrical characterization employs embedded test dies with the 50-Ω ground–signal–ground (GSG) ports and coplanar waveguides. We achieve low-loss die-to-package transitions by using staggered dielectric vias, which are compared with the transitions of wire-bonding and flip-chip assembly. This article provides detailed information on the design, modeling, fabrication, and characterization of the die-to-package interconnects. This article also demonstrates the integration of microstrip patch antenna array and embedded dies in the D-band. The results show superior electrical performance provided by the die-embedded glass interposer. The die-to-package interconnect exhibits good matching (less than —10-dB S11) and low loss (0.2-dB loss) in the D-band. The integrated 1 × 8 patch antenna array shows 11.6-dB broadside gain and good matching with the embedded die. In addition, by using a temporary carrier, the antenna-integrated glass interposer also has great potential for further heterogeneous integration and thermal management.

42 ENGINEERING↗

DOE OSTI2022

Focused Ion Beam Preparation of Low Melting Point Metals: Lessons Learned From Indium

Indium (In) and other low melting point metals are used as interconnects in a variety of hybridized circuits and a full understanding of the metallurgy of these interconnects is important to the reliability and performance of the devices. Here, this paper shows that room temperature focused ion beam (FIB) preparation of cross-sections, using Ga + or Xe + can result in artifacts that obscure the true In microbump structure. The use of modified milling strategies to minimize the increased local sample temperature are shown to produce cross-sections that are representative of the In bump microstructure in some sample configurations. Furthermore, cooling of the sample to cryogenic temperatures is shown to reliably eliminate artifacts in FIB prepared cross-sections of In bumps allowing the true bump microstructure to be observed.

36 MATERIALS SCIENCE↗

DOE OSTI2021

Void-free Copper Electrodeposition in High Aspect Ratio, Full Wafer Thickness Through-Silicon Vias with Endpoint Detection

High density interconnects are required for increased input/output for microelectronics applications, incentivizing the development of Cu electrochemical deposition (ECD) processes for high aspect ratio through-silicon vias (TSVs). This work outlines Cu ECD processes for 62.5 μ m diameter TSVs, etched into a 625 μ m thick silicon substrate, a 10:1 aspect ratio. Cu ECD in high aspect ratio features relies on a delicate balance of electrolyte composition, solution replenishment, and applied voltage. Implementing a CuSO 4 -H 2 SO 4 electrolyte, which contains suppressor and a low chloride concentration, allows for a tunable relationship between applied voltage and localized deposition in the vias. A stepped potential waveform was applied to move the Cu growth front from the bottom of the via to the top. Sample characterization was performed through mechanical cross-sections and X-ray computed tomography (CT) scans. The CT scans revealed small seam voids in the Cu electrodeposit, and process parameters were tuned accordingly to produce void-free Cu features. During the voltage-controlled experiments, measured current data showed a characteristic current minimum, which was identified as an endpoint detection method for Cu deposition in these vias. We believe this is the first report of this novel endpoint detection method for TSV filling.

42 ENGINEERING↗

DOE OSTI2020

Tutorial on forming through-silicon vias

Through-silicon vias (TSVs) are a critical technology for three-dimensional integrated circuit technology. These through-substrate interconnects allow electronic devices to be stacked vertically for a broad range of applications and performance improvements such as increased bandwidth, reduced signal delay, improved power management, and smaller form-factors. There are many interdependent processing steps involved in the successful integration of TSVs. This article provides a tutorial style review of the following semiconductor fabrication process steps that are commonly used in forming TSVs: deep etching of silicon to form the via, thin film deposition to provide insulation, barrier, and seed layers, electroplating of copper for the conductive metal, and wafer thinning to reveal the TSVs. Recent work in copper electrochemical deposition is highlighted, analyzing the effect of accelerator and suppressor additives in the electrolyte to enable void-free bottom-up filling from a conformally lined seed metal.

42 ENGINEERING↗