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Jongeling, Andre

Publications and source records attributed to Jongeling, Andre.

Benchmarking and Testing of Qualcomm Snapdragon System-on-Chip for JPL Space Applications and Missions

As some space missions become more challenging due to new environments, greater distances, or more limited size, weight, and power (SWaP) constraints, spacecraft avionics must adapt to allow the spacecraft to be more autonomous and agile---eliminating the Spacecraft-Earth-Spacecraft feedback loop whenever possible. Prime examples of such missions include Aerobots (such as Ingenuity with extremely low SWaP constraints and demanding signal/image processing during flight) and landers in possibly hostile environments (such as a Europa lander mission, with limited communication capacity, high latency, and constrained power budget). To address these challenges, JPL worked with Qualcomm to demonstrate the use of their Snapdragon 801 system-on-chip (SoC) onboard the Ingenuity Helicopter on Mars. The Qualcomm Snapdragon SoC contains various subsystems, including an ARM cluster, a Graphics processing unit, a Digital Signal Processing subsystem, a Neural Processing Engine, Image Signal Processing subsystem, among others. Since the success of Ingenuity, JPL is continuing to work with Qualcomm to address other applications of the Snapdragon SoC technology. This includes the deployment of two 855 Snapdragon development boards onboard the International Space Station (ISS) for successful in-situ benchmarking of applications in space (beyond those tested on Ingenuity). In this paper, we will examine the performance of various applications that have been identified to benefit from greater onboard computational capability. These applications include (among others): machine vision algorithms that are expected to be critical in autonomous entry-descent-and-landing scenarios and real-time Aerobot flight navigation; Hyperspectral compression algorithms; Synthetic Aperture Radar Processing along with various instrument processing algorithms. We discuss how the infusion of Qualcomm's Snapdragon SoC is capable of enabling missions that may not have been able to achieve their goals with traditional flight computing. In addition, we also show that for some algorithms, the software implementation on the Snapdragon SoC outperforms traditional FPGA implementations.

Cretu, Vlad

Detecting Juno’s ‘Heartbeat’: Communications Support during Critical Events of the Juno Mission

The first section of this paper summarizes the radio systems of the spacecraft, the antennas of the DSN, and signal processing performed in real-time on the ground to support the critical activities. The second section goes into detail on each of the critical events with details of the radio science support and results of each event. Finally, the paper is concluded with a discussion of future planned supports and capabilities of radio science support during critical events.

Jongeling, Andre

A common platform for DSN receiver development

NASA's Deep Space Network is currently updating a number of sub systems within the Signal Processing Centers at its Deep Space Communication Complexes in order to modernize aging equipment in the downlink receivers for telemetry, tracking, radio science, and radio astronomy. To reduce development costs and increase commonality among these traditionally custom-built receivers, the implementation team has developed a flexible architecture built primarily around commercial off-the-shelf hardware compliant with the Micro Telecommunications Computing Architecture (uTCA) specification and commercial high speed 10Gbit Ethernet switches. Custom firmware and software are being developed to perform the required signal processing functions needed to replace the legacy systems in a phased implementation approach which establishes a new digital Intermediate Frequency (IF) signal distribution system first, followed by implementations of various receiver functions as dictated by need. The first of these new receivers, the Open Loop Receiver, will come online in the Fall of 2018. A description of the new architecture, referred to as the “Common Platform”, will be provided followed by an overview of the phased implementation approach and initial OLR performance results.

Navarro, Robert

Spacecraft-to-Earth Communications for Juno and Mars Science Laboratory Critical Events

Deep Space communications typically utilize closed loop receivers and Binary Phase Shift Keying (BPSK) or Quadrature Phase Shift Keying (QPSK). Critical spacecraft events include orbit insertion and entry, descent, and landing.---Low gain antennas--> low signal -to-noise-ratio.---High dynamics such as parachute deployment or spin --> Doppler shift. During critical events, open loop receivers and Multiple Frequency Shift Keying (MFSK) used. Entry, Descent, Landing (EDL) Data Analysis (EDA) system detects tones in real-time.

radio science

Spacecraft-to-Earth communications for Juno and Mars Science Laboratory critical events

This paper describes the Entry, Descent, and Landing (EDL) Data Analysis (EDA) system. The EDA software supports the real-time interpretation of Multiple Frequency-Shift Keying tones provided by the spacecraft. The objective of this software is to provide communication of status between the spacecraft and the mission personnel on Earth during critical events when low rate telemetry is not possible. Although these communications cannot be used to affect the landing due to the length of time required at these distances, this information is important in the case of a mission failure. Mars Science Laboratory (MSL) will utilize the EDA software during EDL. Juno usage will include deep space maneuvers, Jupiter orbital insertion, and its period reduction maneuver. Results are presented from the Juno tones test. Simulated MSL and Juno signals were also generated and these results are analyzed.

Navarro, Robert

Breadboard Signal Processor for Arraying DSN Antennas

A recently developed breadboard version of an advanced signal processor for arraying many antennas in NASA s Deep Space Network (DSN) can accept inputs in a 500-MHz-wide frequency band from six antennas. The next breadboard version is expected to accept inputs from 16 antennas, and a following developed version is expected to be designed according to an architecture that will be scalable to accept inputs from as many as 400 antennas. These and similar signal processors could also be used for combining multiple wide-band signals in non-DSN applications, including very-long-baseline interferometry and telecommunications. This signal processor performs functions of a wide-band FX correlator and a beam-forming signal combiner. [The term "FX" signifies that the digital samples of two given signals are fast Fourier transformed (F), then the fast Fourier transforms of the two signals are multiplied (X) prior to accumulation.] In this processor, the signals from the various antennas are broken up into channels in the frequency domain (see figure). In each frequency channel, the data from each antenna are correlated against the data from each other antenna; this is done for all antenna baselines (that is, for all antenna pairs). The results of the correlations are used to obtain calibration data to align the antenna signals in both phase and delay. Data from the various antenna frequency channels are also combined and calibration corrections are applied. The frequency-domain data thus combined are then synthesized back to the time domain for passing on to a telemetry receiver

Jongeling, Andre

Digital Front End for Wide-Band VLBI Science Receiver

An upgrade to the very-long-baseline-interferometry (VLBI) science receiver (VSR) a radio receiver used in NASA's Deep Space Network (DSN) is currently being implemented. The current VSR samples standard DSN intermediate- frequency (IF) signals at 256 MHz and after digital down-conversion records data from up to four 16-MHz baseband channels. Currently, IF signals are limited to the 265-to-375-MHz range, and recording rates are limited to less than 80 Mbps. The new digital front end, denoted the Wideband VSR, provides improvements to enable the receiver to process wider bandwidth signals and accommodate more data channels for recording. The Wideband VSR utilizes state-of-the-art commercial analog-to-digital converter and field-programmable gate array (FPGA) integrated circuits, and fiber-optic connections in a custom architecture. It accepts IF signals from 100 to 600 MHz, sampling the signal at 1.28 GHz. The sample data are sent to a digital processing module, using a fiber-optic link for isolation. The digital processing module includes boards designed around an Advanced Telecom Computing Architecture (ATCA) industry-standard backplane. Digital signal processing implemented in FPGAs down-convert the data signals in up to 16 baseband channels with programmable bandwidths from 1 kHz to 16 MHz. Baseband samples are transmitted to a computer via multiple Ethernet connections allowing recording to disk at rates of up to 1 Gbps.

Jongeling, Andre