Engineering topics

Jennifer N Downey

Publications and source records attributed to Jennifer N Downey.

3 records

NASA NTRSDate not supplied

Parallelized Convolutional Interleaver Implementation for Efficient DDR Memory Access

Convolutional interleavers are used in many different communications systems to correct for burst errors due to atmospheric fades and scintillation. The interleaver size is related to the channel coherence time and the data rate. Small convolutional interleavers can be implemented in a field programmable gate array (FPGA) block random access memory (BRAM). However, large interleavers exceeding the size of the BRAM on the FPGA are necessary for channels with longer fades and higher data rates. Therefore, an implementation utilizing double data rate (DDR) memory external to the FPGA is necessary. Wide DDR memory data buses can make the use of DDR memory for convolutional interleavers inefficient when individual symbols are written to and read from the memory. DDR memory operational speeds can also limit the data rate of the interleaver. The Consultative Committee for Space Data Systems (CCSDS) Optical Communications High Photon Efficiency (HPE) standard utilizes a convolutional channel symbol interleaver. A previous implementation of the HPE standard utilized BRAM for the convolutional interleaver, but mission requirements for the upcoming Optical Artemis-2 Orion (O2O) communications demonstration dictate the use of an interleaver exceeding the size of the BRAM. An algorithm and method for implementing the convolutional interleaver in the FPGA with DDR memory is described in this paper.

optical communications↗

NASA NTRSDate not supplied

Field-Programmable Gate Array Implementation of a Single Photon-Counting Receive Modem

We present a field-programmable gate array (FPGA) implementation of a single photon-counting receive modem for a pulse position modulated signal. The modem is compliant with the Consultative Committee for Space Data Systems (CCSDS) High Photon Efficiency (HPE) Optical Communications Coding and Synchronization standard and is capable of a maximum data rate of 267 Mbps. The system is designed on a commercial off-the-shelf FPGA platform and utilizes superconducting nanowire single photon counting detectors, analog to digital converters (ADC s) to sample the detectors, and two FPGAs. Symbol timing recovery, photon counting, convolutional deinterleaving, and codeword synchronization areis performed in the first FPGA. The second FPGA performs iterative decoding on each codeword of the serially concatenated pulse position modulated (SCPPM) signal. A digital filter is included to compensate for timing jitter of the detector, and the decoder throughput can be modified adjusted through reconfigurable parallelization. The decoder also implements a resource-efficient, algorithmic polynomial interleaver and deinterleaver. Both FPGAs can be reconfigured to switch between pulse position modulation (PPM)-16 and PPM-32 with code rates 1/3, 1/2, and 2/3. In this paper, we describe the receiver architecture and FPGA implementation of the timing recovery loop and SCPPM decoder, FPGA utilization for the different modes, and receive modem characterization test results.

Field-programmable Gate Array↗

NASA NTRSDate not supplied

A Photon Counting Ground Receiver for Free-Space Optical Communications

The National Aeronautics and Space Administration is developing a photon counting ground receiver for free-space optical communications. The receiver consists of a fiber interconnect, superconducting nanowire single photon counting detectors (SNSPDs), and a field programmable gate array (FPGA) based receive modem. This receiver is compliant with the Consultative Committee for Space Data Systems (CCSDS) Optical Communications High Photon Efficiency standard, which is used in the low photon flux communications regime, including on the upcoming Optical Artemis-2 Orion communications demonstration. The receiver architecture is modular, can be scaled for data rate, and is designed with primarily commercial-off-the-shelf technology. Two fiber interconnect and detector architectures are being prototyped. The first uses a few-mode-fiber coupled to a 16-channel SNSPD array and the second architecture uses a photonic lantern coupled to 7 single-pixel SNSPDs. Photon counting, symbol timing recovery, demodulation and decoding is done using several FPGA cards. This presentation describes the unique features of the ground receiver, performance test results, and challenges with using commercial SNSPDs in free-space optical communications.

Jennifer N Downey↗