Single chip fixed frequency bit synchronizer
A single chip, fixed frequency suboptimum bit synchronizer design which was implemented utilizing a programmable logic device is described. The bit synchronizer is modeled after a digital transition tracking loop for symbol estimation and employs a first-order incremental phase modulator for closed-loop symbol synchronization. The BER and tracking performance is modeled and compared to optimum designs. The bit synchronizer was developed for the Space Shuttle.
Butler, Madeline J.↗