Engineering topics
Heidecker, Jason
Publications and source records attributed to Heidecker, Jason.
Evaluation of Magnetoresistive RAM for Space Applications
Magnetoresistive random-access memory (MRAM) is a non-volatile memory that exploits electronic spin, rather than charge, to store data. Instead of moving charge on and off a floating gate to alter the threshold voltage of a CMOS transistor (creating different bit states), MRAM uses magnetic fields to flip the polarization of a ferromagnetic material thus switching its resistance and bit state. These polarized states are immune to radiation-induced upset, thus making MRAM very attractive for space application. These magnetic memory elements also have infinite data retention and erase/program endurance. Presented here are results of reliability testing of two space-qualified MRAM products from Aeroflex and Honeywell.
Rad-Hard Structured ASIC Body of Knowledge
Structured Application-Specific Integrated Circuit (ASIC) technology is a platform between traditional ASICs and Field-Programmable Gate Arrays (FPGA). The motivation behind structured ASICs is to combine the low nonrecurring engineering costs (NRE) costs of FPGAs with the high performance of ASICs. This report provides an overview of the structured ASIC platforms that are radiation-hardened and intended for space application
MRAM Technology Status
Magnetoresistive Random Access Memory (MRAM) is much different from conventional types of memory like SRAM, DRAM, and Flash, where electric charge is used to store information. Instead of exploiting the charge of an electron, MRAM uses its spin to store data. This new type of electronics is known as “spintronics.” The primary focus of this report is the current generation of MRAM technology, and its reliability, vendors, and space-readiness.
MRAM Technology Status
Magnetoresistive Random Access Memory (MRAM) is much different from conventional types of memory like SRAM, DRAM, and Flash, where electric charge is used to store information. Instead of exploiting the charge of an electron, MRAM uses its spin to store data. This new type of electronics is known as "spintronics." The primary focus of this report is the current generation of MRAM technology, and its reliability, vendors, and space-readiness.
NAND Flash Qualification Guideline
Better performing Forward Error Correction on the forward link along with adequate power in the data open an uplink operations trade space that enable missions to: Command to greater distances in deep space (increased uplink margin). Increase the size of the payload data (latency may be a factor). Provides space for the security header/trailer of the CCSDS Space Data Link Security Protocol. Note: These higher rates could be used for relief of emergency communication margins/rates and not limited to improving top-end rate performance. A higher performance uplink could also reduce the requirements on flight emergency antenna size and/or the performance required from ground stations. Use of a selective repeat ARQ protocol may increase the uplink design requirements but the resultant development is deemed acceptable, due the factor of 4 to 8 potential increase in uplink data rate.
NAND flash screening and qualification guideline for space application
All space missions have a need for nonvolatile memory (NVM), which maintains data integrity when unpowered. Types of NVM include PROM, EEPROM, NOR Flash, and NAND Flash. PROMs, NOR Flash, and EEPROMs are good choices for storing smaller file size data such as boot code or FPGA configurations. These products have excellent data retention characteristics and can reliably store data for years, unpowered, without any data corruption. They can also be read many times without disturbing the data. Another application of NVM is storage of science and engineering data, which requires large of amounts of memory. The highest density memories available today are SDRAM and NAND Flash. However, the power required to operate and store data in NAND Flash is far less than SDRAM. Wherever high density and low power is required, NAND Flash is very attractive.
Flash Memory Reliability: Read, Program, and Erase Latency Versus Endurance Cycling
This report documents the efforts and results of the fiscal year (FY) 2010 NASA Electronic Parts and Packaging Program (NEPP) task for nonvolatile memory (NVM) reliability. This year's focus was to measure latency (read, program, and erase) of NAND Flash memories and determine how these parameters drift with erase/program/read endurance cycling.
NEPP non-volatile memory : FY09 summary report
This report documents the activities and results of the fiscal year 2009 (FY09) funding for the NASA Electronic Parts and Packaging (NEPP) program for non-volatile memory (NVM) devices. The FY09 task was divided into two main efforts: 1. Development of in-house measurement capability for flash devices 2. Reliability characterization of multi-level vs. single-level flash devices The FY09 NEPP Non Volatile Memory study was organized into these two sections in recognition of the continued and increasing importance of NVM to NASA. All NASA missions use NVM for boot code storage and some limited data archiving. Space-grade NVM has lagged commercial NVM development by many orders of magnitude, however. This gap in density only continues to increase as space-grade memories remain constant in the 1–16 Mbit levels, while commercial flash-based devices shrink in size and double in capacity every 18 months. Commercial flash devices are now at the 32 Gbit level, 10,000 times denser than current NASA NVM. This FY marks the beginning of a significant technological transition in NVM for NASA. The aggressive scaling of commercial NVMs has, as a by-product, made some of the flash devices radiation-tolerant enough to be at least considered for low-level radiation environment missions [Irom 2008]. This NEPP task is focused on understanding the reliability and potential future applications of such highly scaled flash memories.
Impact of Device Scaling on Deep Sub-micron Transistor Reliability: A Study of Reliability Trends using SRAM
As microelectronics are scaled in to the deep sub-micron regime, users of advanced technology CMOS, particularly in high-reliability applications, should reassess how scaling effects impact long-term reliability. An experimental based reliability study of industrial grade SRAMs, consisting of three different technology nodes, is proposed to substantiate current acceleration models for temperature and voltage life-stress relationships. This reliability study utilizes step-stress techniques to evaluate memory technologies (0.25mum, 0.15mum, and 0.13mum) embedded in many of today's high-reliability space/aerospace applications. Two acceleration modeling approaches are presented to relate experimental FIT calculations to Mfr's qualification data.