Engineering topics

Gwaltney, David A.

Publications and source records attributed to Gwaltney, David A..

17 records

NASA NTRS2011

Heavy Lift Vehicle (HLV) Avionics Flight Computing Architecture Study

A NASA multi-Center study team was assembled from LaRC, MSFC, KSC, JSC and WFF to examine potential flight computing architectures for a Heavy Lift Vehicle (HLV) to better understand avionics drivers. The study examined Design Reference Missions (DRMs) and vehicle requirements that could impact the vehicles avionics. The study considered multiple self-checking and voting architectural variants and examined reliability, fault-tolerance, mass, power, and redundancy management impacts. Furthermore, a goal of the study was to develop the skills and tools needed to rapidly assess additional architectures should requirements or assumptions change.

Hodson, Robert F.↗

NASA NTRS2006

Time Triggered Protocol (TTP) for Integrated Modular Avionics

Traditional avionics computing systems are federated, with each system provided on a number of dedicated hardware units. Federated applications are physically separated from one another and analysis of the systems is undertaken individually. Integrated Modular Avionics (IMA) takes these federated functions and integrates them on a common computing platform in a tightly deterministic distributed real-time network of computing modules in which the different applications can run. IMA supports different levels of criticality in the same computing resource and provides a platform for implementation of fault tolerance through hardware and application redundancy. Modular implementation has distinct benefits in design, testing and system maintainability. This paper covers the requirements for fault tolerant bus systems used to provide reliable communication between IMA computing modules. An overview of the Time Triggered Protocol (TTP) specification and implementation as a reliable solution for IMA systems is presented. Application examples in aircraft avionics and a development system for future space application are covered. The commercially available TTP controller can be also be implemented in an FPGA and the results from implementation studies are covered. Finally future direction for the application of TTP and related development activities are presented.

Motzet, Guenter↗

NASA NTRS2006

Time Triggered Protocol (TTP) for Integration Modular Avionics (IMA)

This viewgraph presentation is a review of the Time Triggered Protocol, designed to work with NASA's Integrated Safety-Critical Advanced Avionics Communication and Control (ISAACC) system. ISAACC is the product of the Propulsion High-Impact Avionics Technologies (PHIAT) project at NASA Marshall Space Flight Center (MSFC) during FY03 to the end of FY05. The goal is an avionics architecture suitable for control and monitoring of safety critical systems of manned spacecraft. It must be scalable to allow its use in robotic vehicles or launch pad and propulsion test stand monitoring and control systems. The developed IMA should have: a common power supply and rugged chassis for a set of modules, many upgradeable software functions on one module (i.e. processing unit Reduced weight, straightforward update and system integration. It is also important that it have Partitioning and a Memory Management Unit (MMU)

Gwaltney, David A.↗

NASA NTRS2005

A VHDL Core for Intrinsic Evolution of Discrete Time Filters with Signal Feedback

The design of an Evolvable Machine VHDL Core is presented, representing a discrete-time processing structure capable of supporting control system applications. This VHDL Core is implemented in an FPGA and is interfaced with an evolutionary algorithm implemented in firmware on a Digital Signal Processor (DSP) to create an evolvable system platform. The salient features of this architecture are presented. The capability to implement IIR filter structures is presented along with the results of the intrinsic evolution of a filter. The robustness of the evolved filter design is tested and its unique characteristics are described.

Gwaltney, David A.↗

NASA NTRS2005

Enabling the On-Line Intrinsic Evolution of Analog Controllers

The intrinsic evolution of analog controllers to provide closed-loop control of the speed of a DC motor has been previously demonstrated at NASA Marshall Space Flight Center. A side fleet of the evolutionary process is that during evolution there are necessarily poor configurations to be evaluated that could cause damage to the plant. This paper concern the development and implementation of a safe Evolvable Analog Controller (EAC) architecture able to evolve controllers on-line even in the presence of these poor configurations. The EAC concept is discussed and experimental results are presented that show the feasibility of the approach This EAC architecture represents the first in a series of steps required to make deployment of an evolvable controller a reality.

Gwaltney, David A.↗

NASA NTRS2005

Enabling the On-line Intrinsic Evolution of Analog Controllers

The intrinsic evolution of analog controllers to provide closed-loop control of the speed of a DC motor has been previously demonstrated at NASA Marshall Space Flight Center. A side effect of the evolutionary process is that during evolution there are necessarily poor configurations to be evaluated that could cause damage to the plant, This paper concerns the development and implementation of a safe Evolvable Analog Controller (EAC) architecture able to evolve controllers on-line even in the presence of these poor configurations, The EAC concept is discussed and experimental results are presented that show the feasibility of the approach This EAC architecture represents the first in a series of steps required to make deployment of an evolvable controller a reality.

Gwaltney, David A.↗

NASA NTRS2005

A VHDL Core for Intrinsic Evolution of Discrete Time Filters with Signal Feedback

Evolution of a novel low-pass filter design has been presented along with an assessment of its capabilities. (1) Performed well with the two added sines used as input during the evolution. (2) Also performs well when the input includes more sine at frequencies between the two used during evolution. (3) Fails to perform when input is a sine sweep with wider bandwidth. (4) This illustrates the importance of designing the evolutionary process to be representative of the environment that will be seen by the evolved design during deployment. The use of non-standard operators and fewer resources should allow the EMVCore to implement more compact representations of digital filters and to provide fault tolerance by implementing a new solution in the remaining tiles after some are damaged. The EMVCore can be used to implement standard discrete time filters in addition to evolved components.

Gwaltney, David A.↗

NASA NTRS2005

Enabling the On-line Intrinsic Evolution of Analog Controllers

The authors have worked previously on Analog Controllers. Used JPL developed stand alone board level evolvable (SABLE) system as platform controller evolution. SABLE is a hardware platform incorporating the JPL designed second generation field programmable transistor array (FPTA2).

Gwaltney, David A.↗

NASA NTRS2005

The Integrated Safety-Critical Advanced Avionics Communication and Control (ISAACC) System Concept: Infrastructure for ISHM

Integrated System Health Management (ISHM) architectures for spacecraft will include hard real-time, critical subsystems and soft real-time monitoring subsystems. Interaction between these subsystems will be necessary and an architecture supporting multiple criticality levels will be required. Demonstration hardware for the Integrated Safety-Critical Advanced Avionics Communication & Control (ISAACC) system has been developed at NASA Marshall Space Flight Center. It is a modular system using a commercially available time-triggered protocol, ?Tp/C, that supports hard real-time distributed control systems independent of the data transmission medium. The protocol is implemented in hardware and provides guaranteed low-latency messaging with inherent fault-tolerance and fault-containment. Interoperability between modules and systems of modules using the TTP/C is guaranteed through definition of messages and the precise message schedule implemented by the master-less Time Division Multiple Access (TDMA) communications protocol. "Plug-and-play" capability for sensors and actuators provides automatically configurable modules supporting sensor recalibration and control algorithm re-tuning without software modification. Modular components of controlled physical system(s) critical to control algorithm tuning, such as pumps or valve components in an engine, can be replaced or upgraded as "plug and play" components without modification to the ISAACC module hardware or software. ISAACC modules can communicate with other vehicle subsystems through time-triggered protocols or other communications protocols implemented over Ethernet, MIL-STD- 1553 and RS-485/422. Other communication bus physical layers and protocols can be included as required. In this way, the ISAACC modules can be part of a system-of-systems in a vehicle with multi-tier subsystems of varying criticality. The goal of the ISAACC architecture development is control and monitoring of safety critical systems of a manned spacecraft. These systems include spacecraft navigation and attitude control, propulsion, automated docking, vehicle health management and life support. ISAACC can integrate local critical subsystem health management with subsystems performing long term health monitoring. The ISAACC system and its relationship to ISHM will be presented.

Gwaltney, David A.↗

NASA NTRS2003

Intrinsic Hardware Evolution for the Design and Reconfiguration of Analog Speed Controllers for a DC Motor

Evolvable hardware provides the capability to evolve analog circuits to produce amplifier and filter functions. Conventional analog controller designs employ these same functions. Analog controllers for the control of the shaft speed of a DC motor are evolved on an evolvable hardware platform utilizing a second generation Field Programmable Transistor Array (FPTA2). The performance of an evolved controller is compared to that of a conventional proportional-integral (PI) controller. It is shown that hardware evolution is able to create a compact design that provides good performance, while using considerably less functional electronic components than the conventional design. Additionally, the use of hardware evolution to provide fault tolerance by reconfiguring the design is explored. Experimental results are presented showing that significant recovery of capability can be made in the face of damaging induced faults.

Gwaltney, David A.↗

NASA NTRS2003

Hardware Evolution of Analog Speed Controllers for a DC Motor

Gwaltney, David A.↗

NASA NTRS2003

Hardware Evolution of Analog Speed Controllers for a DC Motor

This viewgraph presentation provides information on the design of analog speed controllers for DC motors on aerospace systems. The presentation includes an overview of controller evolution, evolvable controller configuration, an emphasis on proportion integral (PI) controllers, schematic diagrams, and experimental results.

Gwaltney, David A.↗

NASA NTRS2002

Implementation of Adaptive Digital Controllers on Programmable Logic Devices

Much has been made of the capabilities of FPGA's (Field Programmable Gate Arrays) in the hardware implementation of fast digital signal processing (DSP) functions. Such capability also makes and FPGA a suitable platform for the digital implementation of closed loop controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM- based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance in a compact form-factor. Other researchers have presented the notion that a second order digital filter with proportional-integral-derivative (PID) control functionality can be implemented in an FPGA. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using digital signal processor (DSF) devices. Our goal is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive control algorithm approaches. While small form factor, commercial DSP devices are now available with event capture, data conversion, pulse width modulated outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. Meeting our goals requires alternative compact implementation of such functionality to withstand the harsh environment encountered on spacecraft. Radiation tolerant FPGA's are a feasible option for reaching these goals.

Gwaltney, David A.↗

NASA NTRS2002

Implementation of Adaptive Digital Controllers on Programmable Logic Devices

Much has been made of the capabilities of Field Programmable Gate Arrays (FPGA's) in the hardware implementation of fast digital signal processing functions. Such capability also makes an FPGA a suitable platform for the digital implementation of closed loop controllers. Other researchers have implemented a variety of closed-loop digital controllers on FPGA's. Some of these controllers include the widely used Proportional-Integral-Derivative (PID) controller, state space controllers, neural network and fuzzy logic based controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM- based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance requirements in a compact form-factor. Generally, a software implementation on a Digital Signal Processor (DSP) device or microcontroller is used to implement digital controllers. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using DSP devices. While small form factor, commercial DSP devices are now available with event capture, data conversion, Pulse Width Modulated (PWM) outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. In general, very few DSP devices are produced that are designed to meet any level of radiation tolerance or hardness. An alternative is required for compact implementation of such functionality to withstand the harsh environment encountered on spacemap. The goal of this effort is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive-control algorithm approaches. Radiation tolerant FPGA's are a feasible option for reaching this goal.

Gwaltney, David A.↗

NASA NTRS2002

Implementation of Adaptive Digital Controllers on Programmable Logic Devices

Much has been made of the capabilities of FPGA's (Field Programmable Gate Arrays) in the hardware implementation of fast digital signal processing. Such capability also makes an FPGA a suitable platform for the digital implementation of closed loop controllers. Other researchers have implemented a variety of closed-loop digital controllers on FPGA's. Some of these controllers include the widely used proportional-integral-derivative (PID) controller, state space controllers, neural network and fuzzy logic based controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM-based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance requirements in a compact form-factor. Generally, a software implementation on a DSP (Digital Signal Processor) or microcontroller is used to implement digital controllers. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using digital signal processor (DSP) devices. While small form factor, commercial DSP devices are now available with event capture, data conversion, pulse width modulated (PWM) outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. In general, very few DSP devices are produced that are designed to meet any level of radiation tolerance or hardness. The goal of this effort is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive control algorithm approaches. An alternative is required for compact implementation of such functionality to withstand the harsh environment encountered on spacecraft. Radiation tolerant FPGA's are a feasible option for reaching this goal.

Gwaltney, David A.↗

NASA NTRS1994

Application of fuzzy logic to the control of wind tunnel settling chamber temperature

The application of Fuzzy Logic Controllers (FLC's) to the control of nonlinear processes, typically controlled by a human operator, is a topic of much study. Recent application of a microprocessor-based FLC to the control of temperature processes in several wind tunnels has proven to be very successful. The control of temperature processes in the wind tunnels requires the ability to monitor temperature feedback from several points and to accommodate varying operating conditions in the wind tunnels. The FLC has an intuitive and easily configurable structure which incorporates the flexibility required to have such an ability. The design and implementation of the FLC is presented along with process data from the wind tunnels under automatic control.

Gwaltney, David A.↗

NASA NTRS1992

Ground-based implementation and verification of control laws for tethered satellites

Davis and Banerjee (1990) have developed a tethered-spacecraft system model in which out-of-plane librations are damped, using a length-rate control after the tether has been deployed. Attention is presently given to the implementation of such control schemes to prototype hardware designed for space flight. A prototype reel mechanism has been constructed for use in the Getaway Tether Experiment; both the Davis and Banerjee control scheme and a converted tension-control law have been implemented with tether length and length rate available as feedback.

Gwaltney, David A.↗