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Genat, Jean-Francois

Publications and source records attributed to Genat, Jean-Francois.

An Internal ALD-Based High Voltage Divider and Signal Circuit for MCP-based Photodetectors

We describe a pin-less design for the high voltage (HV) resistive divider of the all-glass LAPPD (TM) 8 in,square thin photodetector module. The divider, which distributes high voltage applied to the photocathode to the two micro-channel plates (MCPs) that constitute the amplification stage, is comprised of the two MCPs and three glass mechanical spacers, each of which is coated with a resistive layer using atomic layer deposition (ALD). The three glass grid spacers and the two MCPs form a continuous resistive path between cathode and anode, with the voltages across the MCPs and the spacers determined by the resistance of each. High voltage is applied on an external tab on the top glass window that connects to the photocathode through the metal seal. The DC ground is supplied by microstrips on the bottom glass plate that form the high-bandwidth anode. The microstrips exit the package through the glass-frit seal of the anode base-plate and the package sidewall. The divider is thus completely internal, with no HV pins penetrating the low-profile flat glass package. Measurements of the performance of the divider are presented for the 8 in.-square MCP and spacer package in a custom test fixture and for an assembled externally pumped LAPPD (TM) prototype with an aluminum photocathode. (C) 2015 Elsevier B.V. All rights reserved.

Adams, Bernhard W.↗

A 15GSa/s, 1.5GHz bandwidth waveform digitizing ASIC

The PSEC4 custom integrated circuit was designed for the recording of fast waveforms for use in large-area time-of-flight detector systems. The ASIC has been fabricated using the IBM-8RF 0.13 micron CMOS process. On each of 6 analog channels, PSEC4 employs a switched capacitor array (SCA) 256 samples deep, a ramp-compare ADC with 10.5 bits of DC dynamic range, and a serial data readout with the capability of region-of-interest windowing to reduce dead time. The sampling rate can be adjusted between 4 and 15 Gigasamples/second [GSa/s] on all channels and is servo-controlled on-chip with a low-jitter delay-locked loop (DLL). The input signals are passively coupled on-chip with a -3 dB analog bandwidth of 1.5 GHz. The power consumption in quiescent sampling mode is less than 50 mW/chip; at a sustained trigger and readout rate of 50 kHz the chip draws 100 mW. After fixed-pattern pedestal subtraction, the uncorrected integral non-linearity is 0.15% over an 750 mV dynamic range. With a linearity correction, a full 1 V signal voltage range is available.The sampling timebase has a fixed-pattern non-linearity with an RMS of 13%, which can be corrected for precision waveform feature extraction and timing.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗