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Gautam, Ashish [ORNL]

Publications and source records attributed to Gautam, Ashish [ORNL].

9 records
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DOE OSTI2026

Citation network datasets for benchmarking spiking graph neural networks on experimental neuromorphic hardware

Spiking neural networks (SNNs) running on neuromorphic computers offer an energy-efficient alternative for AI tasks. Recently, spiking graph neural networks (S-GNNs) have been shown to produce encouraging results on benchmark citation network datasets such as Cora, CiteSeer, and PubMed for node classification tasks. These S-GNNs were run on SNN simulators only because they contain up to tens of thousands of neurons and up to millions of synapses, translating poorly to neuromorphic hardware. Therefore, in this paper, we create a suite of benchmark datasets from the CiteSeer dataset that can be accommodated on current neuromorphic hardware platforms. Our contribution consists of a collection of three datasets. First, we have an induced subgraph of CiteSeer, which we call MiniSeer, containing 2110 papers, 3604 binary features, and 6 topics. Second, MicroSeer is a very small dataset consisting of 84 papers, 1227 features, and 6 topics. Lastly, BiteSeer is a collection of 15 binary classification datasets. We present creation of these datasets along with accuracies, running times, and spike counts when simulated. We believe that our results in this paper will be used by the neuromorphic community to benchmark, test, and develop neuromorphic hardware and simulators.

Zhu, Kevin [George Mason University, Virginia]↗
DOE OSTI2026

Predicting Band-Gap of Inorganic Materials Using Neuromorphic Graph Learning

Predicting properties of inorganic materials is a heavily researched topic, with several new prediction approaches emerging as competitors. One such competitor is graph neural networks, which leverage the structure of the graph to aid in the prediction process. In this work, we propose integration of neuromorphic computation into the graph neural network pipeline. We call this approach Neuromorphic Graph Learning (NGL). We utilize the NGL approach to leverage evolutionary algorithms and a novel Spike Pipeline for Raster Analysis (SPIRE) for the prediction of band gap in inorganic materials.

Mulet, Ian [University of Tennessee (UT)]↗
DOE OSTI2026

NeuroCoreX: An Open-Source FPGA-Based Spiking Neural Network Emulator with On-Chip Learning

Spiking Neural Networks (SNNs) are computational models inspired by the event-driven communication and connectivity patterns of biological neural circuits. They enable high energy efficiency and natural support for diverse architectures ranging from layered networks to small-world and graphstructured topologies. In this work, we introduce NeuroCoreX, an open-source, FPGA-based spiking neural network emulator that provides real-time, on-chip learning and flexible network organization. NeuroCoreX supports both feedforward sensory inputs streamed directly from sensors or PCs via UART and recurrent on-chip connectivity, enabling simultaneous processing and learning from external stimuli and internal network dynamics-capabilities rarely available in existing FPGA SNN platforms. The system implements a Leaky Integrate-and-Fire (LIF) neuron model with current-based synapses and supports pair-based STDP learning on both feedforward and recurrent synapses. A lightweight Python interface enables interactive configuration, live monitoring, weight read-back, and experiment control. Importantly, NeuroCoreX is tightly integrated with the SuperNeuroMAT simulator, allowing SNN models to be transferred seamlessly from software to hardware for hardware-in-the-loop development. By combining real-time plasticity, flexible connectivity, and an open-source VHDL implementation, NeuroCoreX provides an extensible and accessible platform for neuromorphic research, algorithm-hardware co-design, and energy-efficient edge intelligence.

Gautam, Ashish [ORNL]↗
DOE OSTI2026

Cross-Domain Reasoning for Neuromorphic Model Design

Designing performant neuromorphic models requires reasoning across neuroscience, neuromorphic computing, and machine learning, making it a natural target for cross-domain hypothesis generation. Our primary contribution is a multi-corpus knowledge graph spanning all three domains, which we show substantially increases cross-domain retrieval novelty over single-corpus baselines. We additionally introduce NeuKReAct, an agentic reasoning framework that iteratively retrieves from this graph and synthesizes design hypotheses via a step-by-step blackboard architecture, enabling structured compartmentalization of design decisions. Lastly, we introduce an execution head that translates hypotheses into structured design documents and runnable code. We evaluate novelty using a combinatorial creativity metric that measures cross-domain retrieval distance across the citation graph. Our results confirm that corpus breadth is the dominant driver of novelty. Moreover, we highlight a concrete instance of the novelty-utility tradeoff within NeuKReAct, underscoring a need for joint creativity evaluation, balancing both novelty and utility.

Ramavarapu, Vikram [ORNL] (ORCID:0009000188757213)↗
DOE OSTI2026

ObstacleSense: Low-Power Neuromorphic Vision for Corridor Obstacle Awareness in Low-Level ADAS

The automotive industry’s pursuit of Level 5 autonomy is constrained by substantial perception-compute power requirements, often reaching 1, 000 + watts in full autonomy stacks. Reducing this energy burden requires rethinking perception not only at the high-end autonomy level, but also at the foundational Advanced Driver Assistance Systems (ADAS) level where low-power, safety-critical sensing can have broad impact. Neuromorphic vision provides a promising starting point: HD Dynamic Vision Sensors (DVS) can operate below 100 mW at the sensor level by reporting only asynchronous brightness changes. However, low-power sensing alone is insufficient if downstream perception reintroduces dense, energy-intensive computation. In particular, many event-driven object-detection pipelines still rely on CNN backbones, while purely spiking alternatives often trade away accuracy or ignore deployment constraints. We introduce ObstacleSense, a highly compact, CNN-free hybrid ANN–SNN framework for Level 0–1 forward-corridor obstacle awareness. Instead of performing full-scene object detection with a convolutional feature backbone, ObstacleSense targets the safety-critical question of whether the ego corridor is occupied and how far the nearest obstacle is. The architecture combines polarity-conditioned event encoding, lightweight temporal spiking dynamics, axial spatial mixing, and coarse-to-fine range estimation within a regular fixed-grid compute pattern. This design avoids the dense CNN backbone commonly used in event-based detection while maintaining a small state footprint suitable for eventual small-FPGA deployment. Before hardware mapping, we evaluate the software implementation using a model-side power proxy derived from MACs, weight and activation traffic, and spiking state updates under shared FP16 assumptions. On simulated CARLA event corpora, the deployment-oriented model achieves 0.9464 objectness F1, 0.9978 grid-level mAP, and 0.8987 m distance Mean Absolute Error at an estimated 1.92 mW proxy cost, while maintaining performance on unseen generalization test sequences.

Johnson-Scott, Zac [ORNL]↗
DOE OSTI2026

A Unidirectional Two-Compartment Neuron Circuit with On-chip STDP learning

Most neuromorphic chips implement the single-compartment point neuron model where synapse circuits connect directly to a leaky integrate and fire (LIF) soma circuit. However, when using a biologically plausible soma circuit (e.g., Hodgkin-Huxley neuron model), an interface circuitry, such as a current conveyor circuit, is needed to transmit synaptic current to the soma circuit. This is especially true for ultra-low power neuron circuits, where membrane capacitance is on the order of 20 fF. This need for an interface circuit arises because the parasitic capacitance and leakage current caused by fabrication mismatch and second-order effects of the output transistors in the synapse circuits can disturb the spiking dynamics of the soma circuit if connected without an interface. Using an interface circuit to isolate the soma’s membrane capacitor from synapses resolves this issue. We propose to use a unidirectional resistor (a transconductance circuit) to connect the synapse and soma circuits instead of conventional current conveyor circuits. Using a biologically plausible spike pattern detection model, we show that the on-chip spike-timing-dependent plasticity (STDP) learning performance of the proposed unidirectional two-compartment neuron circuit is similar to a single-compartment circuit (with a current conveyor as an interface) and additionally, it is more power-efficient and biologically plausible. The chip is fabricated in the Taiwan Semiconductor Manufacturing Company (TSMC) 250 nm technology node and comprises a single neuron circuit.

Gautam, Ashish [ORNL]↗
DOE OSTI2025

AI-Powered Knowledge Graphs for Neuromorphic and Energy-Efficient Computing

The surge in scientific literature obscures breakthroughs and hinders the discovery of new research paths. We propose an artificial intelligence (AI) powered framework using large language models (LLMs) and knowledge graphs (KGs) to automate parts of scientific discovery, focusing on energy-efficient AI circuits. Our hybrid approach combines LLMs, structured data, and ontology-based reasoning to construct a comprehensive knowledge graph that integrates insights across computational neuroscience, spiking neuron models, learning rules, architectural motifs, and neuromorphic device technologies. This multi-domain representation enables the generation of hypotheses that connect biological function with implementable, energy-efficient hardware architectures. Using KG embeddings and graph neural networks, the framework generates hypotheses for novel circuits, validates them through optimization on exascale HPC systems, and with tools like SuperNeuro and Fugu, the most promising designs will be prototyped in hardware. This open-source system aims to accelerate discoveries and bridging neuroscience with hardware innovation, drive collaboration, and unlock new opportunities in low-power AI computing.

Gautam, Ashish [ORNL]↗
DOE OSTI2024

A Suppression-based STDP Rule Resilient to Jitter Noise in Spike Patterns for Neuromorphic Computing

Multi-spike models of synaptic plasticity, such as the triplet and suppression spike-timing-dependent plasticity (STDP) rules, exhibit better alignment with neurophysiological data in the brain compared to the pair-based STDP rule. Previous studies have empirically shown that the pair-based STDP rule can detect spatiotemporal spike patterns hidden in equally dense distractor spike trains in an unsupervised manner. However, it fails to detect spike patterns influenced by jitter noise. Given that spiking neural networks (SNNs) exhibit variability in generated spike trains in response to the same inputs, it becomes imperative to have learning rules capable of detecting spike patterns even in the presence of jitter noise. In this study, we introduce a simplified suppression-based STDP rule that demonstrates significantly enhanced tolerance to jitter in spike patterns compared to the pair-based STDP rule. Unlike the ideal suppression STDP rule, characterized by an exponential learning window and requiring high-resolution synapses, the simplified rule limits the synaptic efficacy update to a single bit at any given instant. Moreover, it employs 4-bit fixed-point synapses, facilitating straightforward implementation in neuromorphic hardware.

Gautam, Ashish [ORNL]↗