Engineering topics

Fong, Wai

Publications and source records attributed to Fong, Wai.

14 records

NASA NTRS2019

Action: Baseline Channel Model for SCCC-X and DVB-S2X

This paper analyzes the impact to the error performance of very high-order modulations, specifically 256APSK and 128APSK, in the DVB-S2X and SCCC-X proposals due to transmitter distortions, i.e. phase and amplitude imbalance, amplification non-linearities, and phase noise. The receiver is assumed to be a matched filter with angle derotation capabilities. An exact theoretical prediction is developed as well as supporting simulations is provided.

Modulation↗

NASA NTRS2018

Performance of Variable Coded Modulations over a Nonlinear Channel for VCM Protocol Red Book

This presentation provides a summary of the results obtained from a study which evaluates the performance of variable coded modulations specified in the "Variable Coded Modulation Protocol" CCSDS Red Book, over a nonlinear channel that is currently on the CCSDS Blue Book track. The objectives are to perform simulation that identifies the operating signal-to-noise-power ratio required to achieve a codeword error rate of 1e-4 over the specified nonlinear channel for various modulations (i.e. BPSK, QPSK, 8-PSK) and LDPC coding schemes, and compare against performance over an ideal additive white Gaussian channel. We select a only subset of operating modes to perform the analysis which are based on a number of mitigation techniques to combat the nonlinear distortions. Specifically, transmitter centroidal pre-distortion, phase post-distortion and receiver mean phase estimation are analyzed in this study.

coding↗

NASA NTRS2017

NASA GSFC Report on CCSDS Recommendations 2.1.8A B Minimum Earth Station Transmitter Frequency Resolution for Spacecraft Receiver Acquisition

In Fall 2016, ESA presented paper SLS-RFM 16-10 documenting a possible issue with the frequency lock-in range specification in Recommendation 2.1.8A of typically 267 to 1067 Hz in considerings (b) from considerings (a) for loop bandwidths [2B(sub LO)] in the range of 200 to 800 Hz with a recommendation of 100 Hz step size for frequency sweeping. The paper calculated the lock-in range to be (+/-)266 to (+/-)1064 rad/s or (+/-)42 to (+/-)168 Hz. Also, Recommendation 2.1.8B has the same issue for considering (a) and (b), i.e. for 2B(sub LO) =10 Hz, a lock-in range of 13 Hz was specified and a recommendation of 5 Hz step size for frequency sweeping. ESA also provided test results from the Rosetta and Exomars transponders. The results were somewhat inconsistent since the tests to verify lock-in and pull-in range did not include acquisition time, which is vital to the definition of these performance measures. This paper will address these test results below. However, we first examine the rationale for Recommendation 2.1.8A/B and its consistency with the theory of 2nd order phase lock loop operations. Our approach is to design a digital phase locked loop (DPLL) from phase locked loop (PLL) requirements. All analysis will be performed with a DPLL.

digital phase locked loop↗

NASA NTRS2012

High Data Rate (Gbps) Coding Architecture

No abstract available

Sank, Victor↗

NASA NTRS2009

Parallel-Processing CMOS Circuitry for M-QAM and 8PSK TCM

There has been some additional development of parts reported in "Multi-Modulator for Bandwidth-Efficient Communication" (NPO-40807), NASA Tech Briefs, Vol. 32, No. 6 (June 2009), page 34. The focus was on 1) The generation of M-order quadrature amplitude modulation (M-QAM) and octonary-phase-shift-keying, trellis-coded modulation (8PSK TCM), 2) The use of square-root raised-cosine pulse-shaping filters, 3) A parallel-processing architecture that enables low-speed [complementary metal oxide/semiconductor (CMOS)] circuitry to perform the coding, modulation, and pulse-shaping computations at a high rate; and 4) Implementation of the architecture in a CMOS field-programmable gate array.

Gray, Andrew↗

NASA NTRS2009

Multi-Modulator for Bandwidth-Efficient Communication

A modulator circuit board has recently been developed to be used in conjunction with a vector modulator to generate any of a large number of modulations for bandwidth-efficient radio transmission of digital data signals at rates than can exceed 100 Mb/s. The modulations include quadrature phaseshift keying (QPSK), offset quadrature phase-shift keying (OQPSK), Gaussian minimum-shift keying (GMSK), and octonary phase-shift keying (8PSK) with square-root raised-cosine pulse shaping. The figure is a greatly simplified block diagram showing the relationship between the modulator board and the rest of the transmitter. The role of the modulator board is to encode the incoming data stream and to shape the resulting pulses, which are fed as inputs to the vector modulator. The combination of encoding and pulse shaping in a given application is chosen to maximize the bandwidth efficiency. The modulator board includes gallium arsenide serial-to-parallel converters at its input end. A complementary metal oxide/semiconductor (CMOS) field-programmable gate array (FPGA) performs the coding and modulation computations and utilizes parallel processing in doing so. The results of the parallel computation are combined and converted to pulse waveforms by use of gallium arsenide parallel-to-serial converters integrated with digital-to-analog converters. Without changing the hardware, one can configure the modulator to produce any of the designed combinations of coding and modulation by loading the appropriate bit configuration file into the FPGA.

Gray, Andrew↗

NASA NTRS2005

A Gigabit-per-Second Ka-Band Demonstration Using a Reconfigurable FPGA Modulator

Gigabit-per-second communications have been a desired target for future NASA Earth science missions, and for potential manned lunar missions. Frequency bandwidth at S-band and X-band is typically insufficient to support missions at these high data rates. In this paper, we present the results of a 1 Gbps 32-QAM end-to-end experiment at Ka-band using a reconfigurable Field Programmable Gate Array (FPGA) baseband modulator board. Bit error rate measurements of the received signal using a software receiver demonstrate the feasibility of using ultra-high data rates at Ka-band, although results indicate that error correcting coding and/or modulator predistortion must be implemented in addition. Also, results of the demonstration validate the low-cost, MOS-based reconfigurable modulator approach taken to development of a high rate modulator, as opposed to more expensive ASIC or pure analog approaches.

reconfigurable↗

NASA NTRS2003

Bandwidth Efficient Baseband Multi-Modulator

The High Rate Baseband Multi-Modulator (HRBM) ASIC is being developed to provide High-speed Bandwidth Efficient Modulations to NASA missions. Bandwidth efficiencies from 2.0 bits/symbol/Hz to 2.75 bits/symbl/Hz are selectable from three CCSDS modulations: Gaussian Minimum Shift Keying (GMSK), Filter Offset Quadrature Phase Shift Keying (Filtered- OQSK) and 8-Phase Shift Keying Trellis Coded Modulation (8-PSK TCM). An FPGA version of the HRBM is developed first to verify the individual modulation designs and characterize timing and performance issues involved with digital baseband modulation synthesis. A Finite Input Response (FIR) filter is included to provided baseband pulse shaping to reduce out-of-band spectral emissions. This is filter is programmable and can be tailored to meet system requirements. The ASIC is targeted to provide up to 600 Mbps throughput and will provide serial as well as parallel input. This paper provides an overview of the technology development and current status.

Fong, Wai↗

NASA NTRS2003

Low Density Parity Check Codes: Bandwidth Efficient Channel Coding

Low Density Parity Check (LDPC) Codes provide near-Shannon Capacity performance for NASA Missions. These codes have high coding rates R=0.82 and 0.875 with moderate code lengths, n=4096 and 8176. Their decoders have inherently parallel structures which allows for high-speed implementation. Two codes based on Euclidean Geometry (EG) were selected for flight ASIC implementation. These codes are cyclic and quasi-cyclic in nature and therefore have a simple encoder structure. This results in power and size benefits. These codes also have a large minimum distance as much as d,,, = 65 giving them powerful error correcting capabilities and error floors less than lo- BER. This paper will present development of the LDPC flight encoder and decoder, its applications and status.

Fong, Wai↗

NASA NTRS2002

Low Resolution Picture Transmission (LRPT) Demonstration System

Low-Resolution Picture Transmission (LRPT) is a proposed standard for direct broadcast transmission of satellite weather images. This standard is a joint effort by the European Organization for the Exploitation of Meteorological Satellites (EUMETSAT) and the National Oceanic Atmospheric Administration (NOAA). As a digital transmission scheme, its purpose is to replace the current analog Automatic Picture Transmission (APT) system for use in the Meteorological Operational (METOP) satellites. Goddard Space Flight Center has been tasked to build an LRPT Demonstration System (LDS). It's main objective is to develop or demonstrate the feasibility of a low-cost receiver utilizing a Personal Computer (PC) as the primary processing component and determine the performance of the protocol in the simulated Radio Frequency (RF) environment. The approach would consist of two phases. In the phase 1, a Commercial-off-the-Shelf (COTS) Modulator-Demodulator (MODEM) board that would perform RF demodulation would be purchased allowing the Central Processing Unit (CPU) to perform the Consultative Committee for Space Data Systems (CCSDS) protocol processing. Also since the weather images are compressed the PC would perform the decompression. Phase 1 was successfully demonstrated on December 1997. Phase 2 consists of developing a high-fidelity receiver, transmitter and environment simulator. Its goal is to find out how the METOP Specification performs in a simulated noise environment in a cost-effective receiver. The approach would be to produce a receiver using as much software as possible to perform front-end processing to take advantage of the latest high-speed PCs. Thus the COTS MODEM used in Phase 1 is performing RF demodulation along with data acquisition providing data to the receiving software. Also, environment simulator is produced using the noise patterns generated by Institute for Telecommunications Sciences (ITS) from their noise environment study.

Fong, Wai↗

NASA NTRS2002

Low Resolution Picture Transmission (LRPT) Demonstration System

Fong, Wai↗

NASA NTRS1994

End-to-end communication test on variable length packet structures utilizing AOS testbed

This paper describes a communication test, which successfully demonstrated the transfer of losslessly compressed images in an end-to-end system. These compressed images were first formatted into variable length Consultative Committee for Space Data Systems (CCSDS) packets in the Advanced Orbiting System Testbed (AOST). The CCSDS data Structures were transferred from the AOST to the Radio Frequency Simulations Operations Center (RFSOC), via a fiber optic link, where data was then transmitted through the Tracking and Data Relay Satellite System (TDRSS). The received data acquired at the White Sands Complex (WSC) was transferred back to the AOST where the data was captured and decompressed back to the original images. This paper describes the compression algorithm, the AOST configuration, key flight components, data formats, and the communication link characteristics and test results.

Miller, Warner H.↗

NASA NTRS1993

A high-speed lossless data compression system for space applications

This paper reports on the integration of a lossless data compression/decompression chipset into a space data system architecture. For its compression engine, the data system incorporates the Universal Source Encoder (USE) designed for the NASA/Goddard Space Flight Center. Currently, the data compression testbed generates video frames consisting of 512 lines of 512 pixels having 8-bit resolution. Each image is passed through the USE where the lines are internally partitioned into 16-word blocks. These blocks are adaptively encoded across widely varying entropy levels using a Rice 12-option set coding algorithm. The current system operates at an Input/Output rate of 10 Msamples/s or 80 Mbits/s for each buffered input line. Frame and line synchronization for each image are maintained through the use of uniquely decodable command words. Length information of each variable length compressed image line is also included in the output stream. The data and command information are passed to the next stage of the system architecture through a serial fiber-optic transmitter. The initial segment of this stage consists of packetizer hardware which adds an appropriate CCSDS header to the received source data. An uncompressed mode is optionally available to pass image lines directly to the packetizer hardware. A data decompression testbed has also been developed to confirm the data compression operation.

Miko, Joe↗

NASA NTRS1989

Real time processor for array speckle interferometry

The authors are constructing a real-time processor to acquire image frames, perform array flat-fielding, execute a 64 x 64 element two-dimensional complex FFT (fast Fourier transform) and average the power spectrum, all within the 25 ms coherence time for speckles at near-IR (infrared) wavelength. The processor will be a compact unit controlled by a PC with real-time display and data storage capability. This will provide the ability to optimize observations and obtain results on the telescope rather than waiting several weeks before the data can be analyzed and viewed with offline methods. The image acquisition and processing, design criteria, and processor architecture are described.

Chin, Gordon↗