TinMan Balloon Flight Presentation to NASA Mission Readiness/ PIR Review
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Engineering topics
Publications and source records attributed to Fairbanks, Thomas D..
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Thermal neutrons have recently become a concern in the semiconductor community where it has been reported that approximately 20% of the single-event upsets are due to thermal neutrons in some devices. The goal of this project is to measure the intensity of thermal neutrons in the High- Performance Computing (HPC) area. This is part of a larger effort to characterize the radiation environment in the HPC area which includes high-energy neutrons as well as thermal neutrons. To accomplish this goal, we designed and fabricated a neutron detector that is sensitive to thermal neutrons called Tin-II. The Tin-II detector consists of two identical 3He ionization chambers with one detector bare and one detector shielded with cadmium. Because the cadmium shielding effectively blocks the thermal neutrons, the difference in count rates between these two detectors reflect the number of thermal neutrons detected. This report summarizes the status of our efforts to develop this detector.
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Commercial microprocessors could be useful computational platforms in space systems, as long as the risk is bound. Many spacecraft are computationally constrained because all of the computation is done on a single radiation-hardened microprocessor. It is possible that a commercial microprocessor could be used for configuration, monitoring and background tasks that are not mission critical. Most commercial microprocessors are affected by radiation, including single-event effects (SEEs) that could be destructive to the component or corrupt the data. Part screening can help designers avoid components with destructive failure modes, and mitigation can suppress data corruption. We have been experimenting with a method for masking radiation-induced faults through the software executing on the microprocessor. While triple-modular redundancy (TMR) techniques are very effective at masking faults in software, the increased amount of execution time to complete the computation is not desirable. Here in this article we present a technique for combining duplication with compare (DWC) with TMR that decreases observable errors by as much as 145 times with only a 2.35 time decrease in performance.
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