Design, Fabrication and Evaluation of Deep Submicron FETs
GaAs FET's with gatelengths on a nanometer scale have been designed, fabricated and evaluated in order to investigate the limits of conventional GaAs scaling rules. An optimum layer structure for deep submicron GaAs MESFET's was designed, and a fabrication process that minimizes the effects of extrinsic parasitics was developed. The fabricated FET's were measured and evaluated at DC and at RF frequencies. 0.1 micron and 50 nm gatelength GaAs MESFET's with 2x45 micron wide "T"-shaped gates were fabricated so that a wide range of saturation current was achieved. For the 0.1 micron gatelength FET's, peak g(sub m,ext) varies from 611 mS/mm to 795 mS/mm with an average value of 717 mS/mm, peak f(sub t) varies from 90 GHz to 103 GHz with an average value of 96 GHz, and peak f(sub max) varies from 147 GHz to 172 GHz with an average value of 161 GHz. In comparison, the peak g(sub m,ext) of the 50 nm gatelength FET's is reduced by almost 20%, the peak f(sub t) is increased by 30%, and the peak f(sub max) is about the same as for the 0.1 micron gatelength FET's. The f(sub t) of the 50 nm gatelength FET's is higher than the f(sub t) of the 0.1 micron gatelength FET's because of the reduced gate-source capacitance (C(sub gs)). The peak f(sub max) does not show a similar improvement because of the onset of short channel effects.