A Multi-Functional Streaming Readout ASIC With Channel-Embedded DSP and Neural Inference
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Engineering topics
Deptuch, Grzegorz W.
Publications and source records attributed to Deptuch, Grzegorz W..
Cryogenic Characterization of a 5-6 GHz LC VCO for CMOS-Quantum Co-Integration
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47 OTHER INSTRUMENTATION↗
Test and characterization of finely segmented pixel CZT detectors for future hard x-ray missions
The NuSTAR (Nuclear Spectroscopic Telescope Array) mission was launched in 2012, and it has successfully deployed the first orbiting telescopes to focus high energy X-ray (3 - 79 keV) light, providing a wealth of new information on high-energy X-rays sources. Follow-up missions, such as the proposed HEX-P, BEST, and FORCE, could perform a deeper black hole census providing a more refined measurement of black hole spins, allowing for greater knowledge about supermassive black holes. Here, these missions are motivated by the recent breakthroughs in the hard X-ray mirror technologies, where mirrors, either made of monolithic silicon segments, or made directly or via replication of shells, demonstrate the feasibility of making hard X-ray mirrors with angular resolutions of 5-10 arc-seconds Half Power Diameter (HPD) compared to the NuSTAR’s 1 arc-minute HPD. Such a high angular resolution requires matched detectors with higher degree of segmentation to fully benefit from the achievable improved spatial resolution. In the above framework, the HEXID ASIC, a novel pixelated front-end suitable for reading out a finely segmented CZT sensor with 150 μm pixel pitch in a hexagonal arrangement has been developed. This readout pixelated chip is capable of processing photon-generated charge packets over a large dynamic range (from 2 keV up to 180 keV), while keeping a low input noise (ENC <20 e - ). In this work, the initial characterization of the ASIC prototype will be presented.
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Testing of a Line Driver With Configurable Pre-Emphasis on Lossy Transmission Lines
Rare-event physics experiments such as the Deep Underground Neutrino Experiment (DUNE) or the next Enriched Xenon Observatory (nEXO) experiment search for rare, low-energy events, detected by sensitive detectors immersed in a cryogenic noble liquid (e.g., liquid argon or xenon). Readout electronics used within such detectors must consume minimal power while operating reliably in cryogenic environments. Furthermore, in the case of nEXO, maximizing the radiopurity of the environment is vital to minimize background noise, thus placing strict limits on the volume of dielectric materials, leading to high-loss data cables spanning distances up to 12 m. Such cables cause high attenuation and intersymbol interference (ISI), resulting in a high bit-error rate (BER). These issues were addressed by developing an integrated line driver with configurable pre-emphasis in a 65-nm CMOS process. The pre-emphasis parameters can be programmed to minimize BER for specific cables and data rates under power constraints. Here, the driver was tested at both room and cryogenic temperatures. In both cases, the output BER was found to be strongly correlated with the pre-emphasis settings. Furthermore, analysis and simulation showed that adapting the pre-emphasis settings based on the incoming bit sequence can further improve performance with minimal changes to the current solution.
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Soft error-mitigating semiconductor design system and associated methods
A soft error-mitigating semiconductor design system and associated methods that tailor circuit design steps to mitigate corruption of data in storage elements (e.g., flip flops) due to Single Events Effects (SEEs). Required storage elements are automatically mapped to triplicated redundant nodes controlled by a voting element that enforces majority-voting logic for fault-free output (i.e., Triple Modular Redundancy (TMR)). Storage elements are also optimally positioned for placement in keeping with SEE-tolerant spacing constraints. Additionally, clock delay insertion (employing either a single global clock or clock triplication) in the TMR specification may introduce useful skew that protects against glitch propagation through the designed device. The resultant layout generated from the TMR configuration may relax constraints imposed on register transfer level (RTL) engineers to make rad-hard designs, as automation introduces TMR storage registers, memory element spacing, and clock delay/triplication with minimal designer input.
Miryala, Sandeep↗
Integration of EDWARD readout architecture in full-field fluorescence imaging detector
Data bandwidth, timing resolution and resource utilization in readouts of radiation detectors are a constant challenge. Event driven solutions are pushing against well-trenched framed solutions. The idea for an asynchronous readout architecture called EDWARD ( E vent- D riven W ith A ccess and R eset D ecoder) was presented at the TWEPP 2021 conference. Here we show the progress of our work which resulted in two chip prototypes. The first one, named 3FI65P1, is a full device with the analog pixel circuitry suited for full-field fluorescence imaging. It is already manufactured, and preliminary results are presented. Finally, the second chip, named EDWARD65P1, contains digital pulse generators with Poisson-exponential distribution in each pixel for extraction of the performance matrix of the EDWARD architecture alone.
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