Engineering topics

Cristoloveanu, Sorin

Publications and source records attributed to Cristoloveanu, Sorin.

5 records

NASA NTRS2011

Four-gate transistor analog multiplier circuit

A differential output analog multiplier circuit utilizing four G.sup.4-FETs, each source connected to a current source. The four G.sup.4-FETs may be grouped into two pairs of two G.sup.4-FETs each, where one pair has its drains connected to a load, and the other par has its drains connected to another load. The differential output voltage is taken at the two loads. In one embodiment, for each G.sup.4-FET, the first and second junction gates are each connected together, where a first input voltage is applied to the front gates of each pair, and a second input voltage is applied to the first junction gates of each pair. Other embodiments are described and claimed.

Mojarradi, Mohammad M.↗

NASA NTRS2009

Complementary Paired G4FETs as Voltage-Controlled NDR Device

It is possible to synthesize a voltage-controlled negative-differential-resistance (NDR) device or circuit by use of a pair of complementary G4FETs (four-gate field-effect transistors). [For more information about G4FETs, please see the immediately preceding article]. As shown in Figure 1, the present voltage-controlled NDR device or circuit is an updated version of a prior NDR device or circuit, known as a lambda diode, that contains a pair of complementary junction field-effect transistors (JFETs). (The lambda diode is so named because its current-versus- voltage plot bears some resemblance to an upper-case lambda.) The present version can be derived from the prior version by substituting G4FETs for the JFETs and connecting both JFET gates of each G4FET together. The front gate terminals of the G4FETs constitute additional terminals (that is, terminals not available in the older JFET version) to which one can apply control voltages VN and VP. Circuits in which NDR devices have been used include (1) Schmitt triggers and (2) oscillators containing inductance/ capacitance (LC) resonant circuits. Figure 2 depicts such circuits containing G4FET NDR devices like that of Figure 1. In the Schmitt trigger shown here, the G4FET NDR is loaded with an ordinary inversion-mode, p-channel, metal oxide/semiconductor field-effect transistor (inversion-mode PMOSFET), the VN terminal of the G4FET NDR device is used as an input terminal, and the input terminals of the PMOSFET and the G4FET NDR device are connected. VP can be used as an extra control voltage (that is, a control voltage not available in a typical prior Schmitt trigger) for adjusting the pinch-off voltage of the p-channel G4FET and thereby adjusting the trigger-voltage window. In the oscillator, a G4FET NDR device is loaded with a conventional LC tank circuit. As in other LC NDR oscillators, oscillation occurs because the NDR counteracts the resistance in the tank circuit. The advantage of this G4FET-NDR LC oscillator over a conventional LC NDR oscillator is that one can apply a time-varying signal to one of the extra control input terminals (VN or VP) to modulate the conductance of the NDR device and thereby amplitude-modulate the output signal.

Mojarradi, Mohammad↗

NASA NTRS2009

Universal programmable logic gate and routing method

An universal and programmable logic gate based on G.sup.4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G.sup.4-FET is also presented. The G.sup.4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.

Fijany, Amir↗

NASA NTRS2007

Using G4FETs as a Data Router for In-Plane Crossing of Signal Paths

Theoretical analysis and some experiments have demonstrated that siliconon- insulator (SOI) 4-gate transistors the type known as G(exp 4)FETs could be efficiently used for in-plane crossing of signal paths. Much of the effort of designing very-large-scale integrated (VLSI) circuits is focused on area-efficient routing of signals. The main source of difficulty in VLSI signal routing is the requirement to prevent crossing, in the same plane, of wires that are meant to be kept electrically insulated from each other. Consequently, it often becomes necessary to design and build VLSI circuits in multiple layers with vias (connections between conductors in different layers at selected locations). Suitable devices that would prevent, or at least sufficiently suppress, undesired electrical coupling (cross-talk) between wires crossing in the same plane would enable compact, simpler implementation complex interconnection networks with in-plane crossings that, heretofore, have not been possible in VLSI circuitry. The use of G4FETs as in-plane signal-crossing devices or routers, in combination with the use of G(exp 4)FETs as universal programmable logic gates, would create opportunities for reducing complexity in VLSI design.

Fijany, Amir↗

NASA NTRS2007

G4-FETs as Universal and Programmable Logic Gates

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

Johnson, Travis↗