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Conway, Adam

Publications and source records attributed to Conway, Adam.

At least 19 records

Three dimensional vertically structured electronic devices

An apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate including a first semiconductor material, an array of three dimensional (3D) structures above the substrate, a sidewall heterojunction layer positioned on at least one vertical sidewall of each 3D structure, and an isolation region positioned between the 3D structures. Each 3D structure includes the first semiconductor material. The sidewall heterojunction layer includes a second semiconductor material, where the first and second semiconductor material have different bandgaps.

Conway, Adam↗

High-power electrically tunable switch

A high-voltage switch, whose operation leverages the speed of electrons to generate the “on” time of the pulse in combination with the speed of light to generate the “off” time of the pulse, is described. In one example, the high-voltage switch includes a first electrode, a second electrode spaced apart from the first electrode, a region of non-absorbing material occupying a portion of the space between the first and second electrodes and allowing a laser pulse to propagate therethrough without substantial absorption, and a region of absorbing material occupying another portion of the space and producing a charged particle cloud upon receiving the laser pulse. The high-voltage switch remains “on” upon the charged particle cloud reaching an electrode and until it has been collected by the electrode, and where the high-voltage switch remains “off” subsequent to the collection and until another generated charged particle cloud reaches the electrode.

Voss, Lars↗

Pulse compression photoconductive semiconductor switches

A photoconductive switch that uses materials that support negative differential mobility, whose operation leverages the pulse compression of a charge could to generate the “on” time of the pulse in combination with the speed of light to generate the “off” time of the pulse, is described. In one example, a method of operating a photoconductive switch, which includes two electrodes and a light absorbing material positioned therebetween, includes selecting a value for one or more parameters comprising a voltage for generation of an electric field, a spot size of a laser pulse, a temporal pulse width of the laser pulse, or an intensity of the laser pulse, wherein the selected value(s) for the one or more parameters enable the switch to operate in a region where the light absorbing material exhibits negative differential mobility, and illuminating the light absorbing material with the laser pulse to generate a charge cloud within the light absorbing material.

Voss, Lars F.↗

Three dimensional vertically structured electronic devices

In one embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate comprising a semiconductor material, an array of three dimensional (3D) structures above the substrate, a gate region, and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, the second region including a portion of at least one vertical sidewall of the 3D structure. The gate region is present on a portion of an upper surface of the second region and the gate region is coupled to a portion of the at least one vertical sidewall of each 3D structure.

Conway, Adam↗

Illumination frustums for photoconductive switches

Methods and devices for illuminating a photoconductive switch consisting of an optically actuated photoconductive material situated between two electrodes are described. Light from a light source is coupled to an optical fiber, which is attached to a frustum, the other side of which is proximate to the photoconductive switch. Light from the optical fiber enters the frustum, spreads out, and enters the photoconductive switch via the top-side electrode. Some of the light is absorbed, while the remaining light reflects off the bottom-side electrode, travels back through the photoconductive switch, and any unabsorbed light reenters the frustum. The geometry of the frustum is configured such that most of the light reflects back into the switch itself with only a negligible fraction escaping from the optical fiber, which advantageously results in near total utilization of the light.

Rushford, Michael↗

Design considerations for gallium arsenide pulse compression photoconductive switch

In this paper, we present the physics and design-space exploration of a novel pulse compression photoconductive switch (PCPS) using semi-insulating gallium arsenide (GaAs) operating in the negative differential mobility (NDM) regime of electron transport. We systematically quantify the relationship between the PCPS performance and various design options, including contact separation, laser energy and placement, and trap dynamics. Specifically, we report the full-width at half-maximum and the peak output current generated by the PCPS as a function of applied electrical and optical bias. We discuss the optimal spacing between the electrodes and the distance of the laser spot to the anode to achieve higher electron confinement and superior radio-frequency (RF) metrics. Reducing the laser energy is important to prevent the appearance of secondary peaks due to diffusive transport, but there exists a trade-off between the bandwidth and the maximum current of the PCPS. We also compare the PCPS response with and without trap dynamics and find that the electrostatic screening from the trap-induced space charge is time-independent when the trapping time constant is set larger than the recombination lifetime. Overall, trap dynamics are detrimental to performance, unless the compensation doping scheme to achieve semi-insulating GaAs is carefully selected. Results presented in this paper can be used by experimentalists to fine-tune the PCPS design parameters to meet the specifications of various RF applications. Moreover, our results will provide a strong theoretical basis to the measurements of PCPS devices using GaAs and other NDM materials under investigation.

42 ENGINEERING↗

Three dimensional vertically structured electronic devices

In one embodiment, a method of forming a vertical transistor includes forming a layer comprising a semiconductor material above a substrate, defining three dimensional (3D) structures in the layer, forming a second region in at least one vertical sidewall of each 3D structure, and forming an isolation region between the 3D structures. In another embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate comprising a semiconductor material, an array of 3D structures above the substrate, and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, the second region including a portion of at least one vertical sidewall of the 3D structure.

Conway, Adam↗

Three dimensional vertically structured electronic devices

According to one embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate including a semiconductor material; an array of three dimensional (3D) structures above the substrate; and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, where the second region includes a portion of at least one vertical sidewall of the 3D structure.

Conway, Adam↗

Three dimensional vertically structured MISFET/MESFET

According to one embodiment, an apparatus includes a substrate, and at least one three dimensional (3D) structure above the substrate. The substrate and the 3D structure each include a semiconductor material. The 3D structure also includes: a first region having a first conductivity type, and a second region coupled to a portion of at least one vertical sidewall of the 3D structure.

24 POWER TRANSMISSION AND DISTRIBUTION↗

Three-dimensional co-axial linear photonic switch

Techniques, systems, and devices are disclosed that relate to coaxial photoconductive switch modules. The coaxial photoconductive switch may include an outer conductor, an inner conductor, and a photoconductive material positioned between the inner conductor and the outer conductor. The inner conductor, the outer conductor, and the photoconductive material have a predetermined height. A bias voltage may be applied between the inner conductor and the outer conductor. When light of a predetermined wavelength and a predetermined intensity is incident on the photoconductive material, the photoconductive material may break down allowing a current to flow through the photoconductive material between the inner conductor and the outer conductor.

Conway, Adam↗

Three-dimensional co-axial linear photonic switch

Techniques, systems, and devices are disclosed that relate to coaxial photoconductive switch modules. The coaxial photoconductive switch may include an outer conductor, an inner conductor, and a photoconductive material positioned between the inner conductor and the outer conductor. The inner conductor, the outer conductor, and the photoconductive material have a predetermined height. A bias voltage may be applied between the inner conductor and the outer conductor. When light of a predetermined wavelength and a predetermined intensity is incident on the photoconductive material, the photoconductive material may break down allowing a current to flow through the photoconductive material between the inner conductor and the outer conductor.

Conway, Adam↗

Reliable electrical contacts for high power photoconductive switches

A photoconductive switch consisting of an optically actuated photoconductive material, e.g. a wide bandgap semiconductor such as SiC, situated between opposing electrodes. The electrodes are created using various methods in order to maximize reliability by reducing resistive heating, current concentrations and filamentation, and heating and ablation due to the light source. This is primarily accomplished by the configuration of the electrical contact geometry, choice of contacts metals, annealing, ion implantation, creation of recesses within the SiC, and the use of coatings to act as encapsulants and anti-reflective layers.

42 ENGINEERING↗

Rapid pulse annealing of CdZnTe detectors for reducing electronic noise

A combination of doping, rapid pulsed optical and/or thermal annealing, and unique detector structure reduces or eliminates sources of electronic noise in a CdZnTe (CZT) detector. According to several embodiments, methods of forming a detector exhibiting minimal electronic noise include: pulse-annealing at least one surface of a detector comprising CZT for one or more pulses, each pulse having a duration of .about.0.1 seconds or less. The at least one surface may optionally be ion-implanted. In another embodiment, a CZT detector includes a detector surface with two or more electrodes operating at different electric potentials and coupled to the detector surface; and one or more ion-implanted CZT surfaces on or in the detector surface, each of the one or more ion-implanted CZT surfaces being independently connected to one of the two or more electrodes and the surface of the detector. At least two of the ion-implanted surfaces are in electrical contact.

47 OTHER INSTRUMENTATION↗

Capacitance reduction for pillar structured devices

In one embodiment, an apparatus includes: a first layer including a n+ dopant or p+ dopant; an intrinsic layer formed above the first layer, the intrinsic layer including a planar portion and pillars extending above the planar portion, cavity regions being defined between the pillars; and a second layer deposited on a periphery of the pillars thereby forming coated pillars, the second layer being substantially absent on the planar portion of the intrinsic layer between the coated pillars. The second layer includes an n+ dopant when the first layer includes a p+ dopant. The second layer includes a p+ dopant when the first layer includes an n+ dopant. The apparatus includes a neutron sensitive material deposited between the coated pillars and above the planar portion of the intrinsic layer. In additional embodiments, an upper portion of each of the pillars includes a same type of dopant as the second layer.

36 MATERIALS SCIENCE↗

Three dimensional strained semiconductors

In one embodiment, an apparatus includes a three dimensional structure comprising a semiconductor material, and at least one thin film in contact with at least one exterior surface of the three dimensional structure for inducing a strain in the structure, the thin film being characterized as providing at least one of: an induced strain of at least 0.05%, and an induced strain in at least 5% of a volume of the three dimensional structure. In another embodiment, a method includes forming a three dimensional structure comprising a semiconductor material, and depositing at least one thin film on at least one surface of the three dimensional structure for inducing a strain in the structure, the thin film being characterized as providing at least one of: an induced strain of at least 0.05%, and an induced strain in at least 5% of a volume of the structure.

36 MATERIALS SCIENCE↗

Stress reduction for pillar filled structures

According to one embodiment, an apparatus for detecting neutrons includes an array of pillars, wherein each of the pillars comprises a rounded cross sectional shape where the cross section is taken perpendicular to a longitudinal axis of the respective pillar, a cavity region between each of the pillars, and a neutron sensitive material located in each cavity region.

42 ENGINEERING↗