A mid-circuit erasure check on a dual-rail cavity qubit using the joint-photon number-splitting regime of circuit QED
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Engineering topics
Publications and source records attributed to Chapman, Benjamin J..
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The design of quantum hardware that reduces and mitigates errors is essential for practical quantum error correction (QEC) and useful quantum computation. To this end, we introduce the circuit-Quantum Electrodynamics (QED) dual-rail qubit in which our physical qubit is encoded in the single-photon subspace, { | 01 〉 , | 10 〉 } , of two superconducting microwave cavities. The dominant photon loss errors can be detected and converted into erasure errors, which are in general much easier to correct. In contrast to linear optics, a circuit-QED implementation of the dual-rail code offers unique capabilities. Using just one additional transmon ancilla per dual-rail qubit, we describe how to perform a gate-based set of universal operations that includes state preparation, logical readout, and parametrizable single and two-qubit gates. Moreover, first-order hardware errors in the cavities and the transmon can be detected and converted to erasure errors in all operations, leaving background Pauli errors that are orders of magnitude smaller. Hence, the dual-rail cavity qubit exhibits a favorable hierarchy of error rates and is expected to perform well below the relevant QEC thresholds with today’s coherence times.
Bosonic quantum error correction has proven to be a successful approach for extending the coherence of quantum memories, but to execute deep quantum circuits, high-fidelity gates between encoded qubits are needed. To that end, we present a family of error-detectable two-qubit gates for a variety of bosonic encodings. From a new geometric framework based on a “Bloch sphere” of bosonic operators, we construct ZZ L (θ) and exponential-swap(θ) gates for the binomial, four-legged cat, dual-rail, and several other bosonic codes. The gate Hamiltonian is simple to engineer, requiring only a programmable beam splitter between two bosonic qubits and an ancilla dispersively coupled to one qubit. This Hamiltonian can be realized in circuit QED hardware with ancilla transmons and microwave cavities. The proposed theoretical framework was developed for circuit QED but is generalizable to any platform that can effectively generate this Hamiltonian. Crucially, one can also detect first-order errors in the ancilla and the bosonic qubits during the gates. We show that this allows one to reach error-detected gate fidelities at the 0.01% level with today’s hardware, limited only by second-order hardware errors.
Dielectric loss is known to limit state-of-the-art superconducting qubit lifetimes. Recent experiments imply upper bounds on bulk dielectric loss tangents on the order of 100 parts per billion but because these inferences are drawn from fully fabricated devices with many loss channels, these experiments do not definitely implicate or exonerate the dielectric. To resolve this ambiguity, we devise a measurement method capable of separating and resolving bulk dielectric loss with a sensitivity at the level of 5 ×10 –9 . The method, which we call the dielectric dipper, involves the in situ insertion of a dielectric sample into a high-quality microwave cavity mode. Smoothly varying the participation of the sample in the cavity mode enables a differential measurement of the dielectric loss tangent of the sample. The dielectric dipper can probe the low-power behavior of dielectrics at cryogenic temperatures and does so without the need for any lithographic process, enabling controlled comparisons of substrate materials and processing techniques. We demonstrate the method with measurements of sapphire grown by edge-defined film-fed growth (EFG) in comparison to high-grade sapphire grown by the heat-exchanger method (HEMEX). For EFG sapphire, we infer a bulk loss tangent of 63(8) ×10 –9 and a substrate-air interface loss tangent of 15(3) ×10 –4 (assuming a sample surface thickness of 3 nm). For a typical transmon, this bulk loss tangent would limit device quality factors to Q ≲20 ×10 6 , suggesting that bulk loss is likely the dominant loss mechanism in the longest-lived transmons on sapphire. We also demonstrate this method on HEMEX sapphire and bound its bulk loss tangent to be less than 19(6) ×10 –9 . As this bound is about 3 times smaller than the bulk loss tangent of EFG sapphire, the use of HEMEX sapphire as a substrate would lift the bulk dielectric coherence limit of a typical transmon qubit to several milliseconds.