Engineering topics
Publications and source records attributed to Carl, C. C..
Actual tests with second-order digital phase-locked loop at simulated relative Doppler shift of 1x0.0001 produced phase lock with timing error of 6.5 deg and no appreciable Doppler bias. Loop thus appears to achieve subcarrier synchronization and to remove bias due to Doppler shift in range of interest.
System, fabricated of highly-reliable digital logic elements, operates on binary pulse-code-modulated signals and derives internal synchronization from data signal. All-digital implementation of detector develops synchronization from data signal by computer cross-correlation of command modulation signal with its expected forms in sequence and adjusts detector phases in accordance with correlation peaks.