Engineering topics
Publications and source records attributed to Canaris, J..
Test results for three SEU logic/circuit hardened CMOS memory circuits verify upset and latch-up immunity for two configurations to be in excess of 120 MeV cm(exp 2)/mg using a commercial, non-radiation hardened CMOS process. Test chips from three separate fabrication runs in two different process were evaluated.
A new logic family, which is immune to single event upsets, is described. Members of the logic family are capable of recovery, regardless of the shape of the upsetting event. Glitch propagation from an upset node is also blocked. Logic diagrams for an Inverter, Nor, Nand, and Complex Gates are provided. The logic family can be implemented in a standard, commercial CMOS process with no additional masks. DC, transient, static power, upset recovery and layout characteristics of the new family, based on a commercial 1 micron CMOS N-Well process, are described.
A cellular logic array is described for squaring binary numbers. This array offers a significant increase in speed, with a relatively small hardware overhead. This improvement is a result of novel implementation of the formula (x + y)exp 2 = x(exp 2) + y(exp 2) + 2(x)(y). These results can also be incorporated in the existing arrays achieving considerable hardware reduction.
This paper reports a design technique to harden CMOS memory circuits against Single Event Upset (SEU) in the space environment. A RAM cell and Flip Flop design are presented to demonstrate the method. The Flip Flop was used in the control circuitry for a Reed Solomon encoder designed for the Space Station.
A full custom, 25 MHz, 1.6 microns CMOS Correlator chip is presented. The 5.15mm by 4.23mm chip performs either autocorrelation or crosscorrelation, consuming less than 10mW per channel. The correlator, designed for a space borne spectrometer, contains 32 channels. The 24 bit accumulator registers can be read independent of the input data path, in either 8 bit bytes, or 16 bit words. The device is cascadable and allows integration periods of up to 1.78 seconds, at 25 Megasamples/second. The controllers, for the input data path and the data output section, are implemented with Sequence Invariant State Machines.
A computer aided design (CAD) tool for the design of very large scale integration (VLSI) synchronous sequential controllers is presented. Both the design and layout of the state machine are automatically generated. The program is process independent allowing a choice of design rules to base generation upon. An incremental layout creation approach was implemented which makes the tool useful in a wide range of layout applications. Flow table descriptions are input to characterize the desired machine and a layout archive is output.
A high performance video image processor has been implemented which is capable of grouping contiguous pixels from a raster scan image into groups and then calculating centroid information for each object in a frame. The algorithm employed to group pixels is very efficient and is guaranteed to work properly for all convex shapes as well as most concave shapes. Processing speeds are adequate for real time processing of video images having a pixel rate of up to 20 million pixels per second. Pixels may be up to 8 bits wide. The processor is designed to interface directly to a transputer serial link communications channel with no additional hardware. The full custom VLSI processor was implemented in a 1.6 mu m CMOS process and measures 7200 mu m on a side.
A highly efficient error correcting code has been selected by NASA as a CCSDS standard: the 16 symbol error correcting Reed Solomon code. A VLSI implementation of this decoder is described in this paper. A total of 4 full custom VLSI chips are needed that correct data in real time at an sustained rate of up to 80 Mbits/second.
This paper reports a single 8.2mm by 8.4mm, 200,000 transistor CMOS chip implementation of the Reed Solomon code required by the Space Telescope. The chip features a 10 MHz sustained byte rate independent of error pattern. The 1.6 micron CMOS integrated circuit has complete decoder and encoder functions and uses a single data/system clock. Block lengths up to 255 bytes as well as shortened codes are supported with no external buffering. Erasure corrections as well as random error corrections are supported with programmable corrections of up to 10 symbol errors. Correction time is independent of error pattern and the number of errors.
Conditional sum and binary lookahead carry are two methods for performing fast binary addition. These methods are quite different, but the adders have a common feature that makes them interesting to compare. Both adders have the carry generating logic implemented as a binary tree, which grows in depth as log(sub 2) n,n equals the number of bits in the adder. The delay in the carry paths also grows in proportion to log(sub 2) n. This paper shows that the Transmission-Gate Conditional-Sum adder and the binary lookahead carry adder have the same speed of addition, but that the conditional sum adder requires only 46 percent of the area.