Engineering topics

Bronevetsky, Greg

Publications and source records attributed to Bronevetsky, Greg.

5 records

DOE OSTI2015

Evaluating Application Resilience with XRay

The rising count and shrinking feature size of transistors within modern computers is making them increasingly vulnerable to various types of soft faults. This problem is especially acute in high-performance computing (HPC) systems used for scientific computing, because these systems include many thousands of compute cores and nodes, all of which may be utilized in a single large-scale run. The increasing vulnerability of HPC applications to errors induced by soft faults is motivating extensive work on techniques to make these applications more resilient to such faults, ranging from generic techniques such as replication or checkpoint/restart to algorithm-specific error detection and tolerance techniques. Effective use of such techniques requires a detailed understanding of how a given application is affected by soft faults to ensure that (i) efforts to improve application resilience are spent in the code regions most vulnerable to faults and (ii) the appropriate resilience technique is applied to each code region. This paper presents XRay, a tool to view the application vulnerability to soft errors, and illustrates how XRay can be used in the context of a representative application. In addition to providing actionable insights into application behavior XRay automatically selects the number of fault injection experiments required to provide an informative view of application behavior, ensuring that the information is statistically well-grounded without performing unnecessary experiments.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2014

Detailed Modeling and Evaluation of a Scalable Multilevel Checkpointing System

High-performance computing (HPC) systems are growing more powerful by utilizing more components. As the system mean time before failure correspondingly drops, applications must checkpoint frequently to make progress. But, at scale, the cost of checkpointing becomes prohibitive. A solution to this problem is multilevel checkpointing, which employs multiple types of checkpoints in a single run. Moreover, lightweight checkpoints can handle the most common failure modes, while more expensive checkpoints can handle severe failures. We designed a multilevel checkpointing library, the Scalable Checkpoint/Restart (SCR) library, that writes lightweight checkpoints to node-local storage in addition to the parallel file system. We present probabilistic Markov models of SCR's performance. We show that on future large-scale systems, SCR can lead to a gain in machine efficiency of up to 35 percent, and reduce the load on the parallel file system by a factor of two. In addition, we predict that checkpoint scavenging, or only writing checkpoints to the parallel file system on application termination, can reduce the load on the parallel file system by 20 × on today's systems and still maintain high application efficiency.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2013

Compositional Dataflow Via Abstract Transition Systems

Despite decades of research and development of dataflow analyses within dozens of different compiler infrastructures, analysis of real programs is intractable in practice. The reason is that although a single research group is equipped to model a single well-defined aspect of application behavior, application developers use a very wide range of abstractions and coding techniques within a single application. Since to analyze even a single application all of its complexities must be modeled, researchers must combine analyses from multiple groups into comprehensive analysis frameworks such as OpenAnalysis or LLVM. Analysis composition is expensive in practice, requiring development effort that is quadratic in the number of analyses as well as tight inter-group coordination to maintain consistent APIs to each other’s symbolic abstractions. This paper proposes an approach to building compiler analysis frameworks that simplifies the composition of independently-developed analyses. It formalizes the operation of dataflow analyses in a way that simplifies reasoning about various types of analysis composition. Further, it defines a portable abstraction that can represent the results of many real analyses, making it possible for different analyses to leverage each other’s results with no knowledge of their APIs or internal abstractions and without any coordination between the groups that developed them. We have developed the Fuse compositional analysis framework based on this abstraction, and integrated it in the ROSE [15] compilation system. Our experience is that this approach greatly simplifies composition of program analyses, making it easy to tailor different combinations of program analyses to different input programs.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2013

Active Measurement of the Impact of Network SwitchUtilization on Application Performance

Inter-node networks are a key capability of High-Performance Computing (HPC) systems that differentiates them from less capable classes of machines. However, in spite of their very high performance, the increasing computational power of HPC compute nodes and the associated rise in application communication needs make network performance a common performance bottleneck. To achieve high performance in spite of network limitations application developers require tools to measure their applications’ network utilization and inform them about how the network’s communication capacity relates to the performance of their applications. This paper presents a new performance measurement and analysis methodology based on empirical measurements of network behavior. Our approach uses two benchmarks that inject extra network communication. The first probes the fraction of the network that is utilized by a software component (an application or an individual task) to determine the existence and severity of network contention. The second aggressively injects network traffic while a software component runs to evaluate its performance on less capable networks or when it shares the network with other software components. We then combine the information from the two types of experiment to predict the performance slowdown experienced by multiple software components (e.g. multiple processes of a single MPI application) when they share a single network. Our methodology is applied to individual network switches and demonstrated on two real systems with different types of switches and compute node architectures.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2013

Active Measurement of Memory Resource Consumption

Hierarchical memory is a cornerstone of modern hardware design because it provides high memory performance and capacity at a low cost. However, the use of multiple levels of memory and complex cache management policies makes it very difficult to optimize the performance of applications running on hierarchical memories. As the number of compute cores per chip continues to rise faster than the total amount of available memory, applications will become increasingly starved for memory storage capacity and bandwidth, making the problem of performance optimization even more critical. We propose a new methodology for measuring and modeling the performance of hierarchical memories in terms on the application’s utilization of the key memory resources: capacity of a given memory level and bandwidth between two levels. This is done by actively interfering with the application’s use of these resources. The application’s sensitivity to reduced resource availability is measured by observing the effect of interference on application performance. The resulting resource-oriented model of performance both greatly simplifies application performance analysis and makes it possible to predict an application’s performance when running with various resource constraints. This is useful to predict performance for future memory-constrained architectures.

97 MATHEMATICS AND COMPUTING↗