Engineering topics

Berkun, Andrew

Publications and source records attributed to Berkun, Andrew.

6 records

NASA NTRS2009

Board Saver for Use with Developmental FPGAs

A device denoted a board saver has been developed as a means of reducing wear and tear of a printed-circuit board onto which an antifuse field programmable gate array (FPGA) is to be eventually soldered permanently after a number of design iterations. The need for the board saver or a similar device arises because (1) antifuse-FPGA design iterations are common and (2) repeated soldering and unsoldering of FPGAs on the printed-circuit board to accommodate design iterations can wear out the printed-circuit board. The board saver is basically a solderable/unsolderable FPGA receptacle that is installed temporarily on the printed-circuit board. The board saver is, more specifically, a smaller, square-ring-shaped, printed-circuit board (see figure) that contains half via holes one for each contact pad along its periphery. As initially fabricated, the board saver is a wider ring containing full via holes, but then it is milled along its outer edges, cutting the via holes in half and laterally exposing their interiors. The board saver is positioned in registration with the designated FPGA footprint and each via hole is soldered to the outer portion of the corresponding FPGA contact pad on the first-mentioned printed-circuit board. The via-hole/contact joints can be inspected visually and can be easily unsoldered later. The square hole in the middle of the board saver is sized to accommodate the FPGA, and the thickness of the board saver is the same as that of the FPGA. Hence, when a non-final FPGA is placed in the square hole, the combination of the non-final FPGA and the board saver occupy no more area and thickness than would a final FPGA soldered directly into its designated position on the first-mentioned circuit board. The contact leads of a non-final FPGA are not bent and are soldered, at the top of the board saver, to the corresponding via holes. A non-final FPGA can readily be unsoldered from the board saver and replaced by another one. Once the final FPGA design has been determined, the board saver can be unsoldered from the contact pads on the first-mentioned printed-circuit board and replaced by the final FPGA.

Berkun, Andrew↗

NASA NTRS2009

Interference-Detection Module in a Digital Radar Receiver

A digital receiver in a 1.26-GHz spaceborne radar scatterometer now undergoing development includes a module for detecting radio-frequency interference (RFI) that could contaminate scientific data intended to be acquired by the scatterometer. The role of the RFI-detection module is to identify time intervals during which the received signal is likely to be contaminated by RFI and thereby to enable exclusion, from further scientific data processing, of signal data acquired during those intervals. The underlying concepts of detection of RFI and rejection of RFI-contaminated signal data are also potentially applicable in advanced terrestrial radio receivers, including software-defined radio receivers in general, receivers in cellular telephones and other wireless consumer electronic devices, and receivers in automotive collision-avoidance radar systems.

Fischman, Mark↗

NASA NTRS2007

Ka-Band Radar Terminal Descent Sensor

The terminal descent sensor (TDS) is a radar altimeter/velocimeter that improves the accuracy of velocity sensing by more than an order of magnitude when compared to existing sensors. The TDS is designed for the safe planetary landing of payloads, and may be used in helicopters and fixed-wing aircraft requiring high-accuracy velocity sensing

Pollard, Brian↗

NASA NTRS2004

Improved Timing Scheme for Spaceborne Precipitation Radar

An improved timing scheme has been conceived for operation of a scanning satellite-borne rain-measuring radar system. The scheme allows a real-time-generated solution, which is required for auto targeting. The current timing scheme used in radar satellites involves pre-computing a solution that allows the instrument to catch all transmitted pulses without transmitting and receiving at the same time. Satellite altitude requires many pulses in flight at any time, and the timing solution to prevent transmit and receive operations from colliding is usually found iteratively. The proposed satellite has a large number of scanning beams each with a different range to target and few pulses per beam. Furthermore, the satellite will be self-targeting, so the selection of which beams are used will change from sweep to sweep. The proposed timing solution guarantees no echo collisions, can be generated using simple FPGA-based hardware in real time, and can be mathematically shown to deliver the maximum number of pulses per second, given the timing constraints. The timing solution is computed every sweep, and consists of three phases: (1) a build-up phase, (2) a feedback phase, and (3) a build-down phase. Before the build-up phase can begin, the beams to be transmitted are sorted in numerical order. The numerical order of the beams is also the order from shortest range to longest range. Sorting the list guarantees no pulse collisions. The build-up phase begins by transmitting the first pulse from the first beam on the list. Transmission of this pulse starts a delay counter, which stores the beam number and the time delay to the beginning of the receive window for that beam. The timing generator waits just long enough to complete the transmit pulse plus one receive window, then sends out the second pulse. The second pulse starts a second delay counter, which stores its beam number and time delay. This process continues until an output from the first timer indicates there is less than one transmit pulse width until the start of the next receive event. This blocks future transmit pulses in the build-up phase. The feedback phase begins with the first timer paying off and starting the first receive window. When the first receive window is complete, the timing generator transmits the next beam from the list. When the second timer pays off, the second receive event is started. Following the second receive event, the timing generator will transmit the next beam on the list and start an additional timer. The timers work in a circular buffer fashion so there only need to be enough to cover the maximum number of echoes in flight.

Berkun, Andrew↗

NASA NTRS2004

Digital Radar-Signal Processors Implemented in FPGAs

High-performance digital electronic circuits for onboard processing of return signals in an airborne precipitation- measuring radar system have been implemented in commercially available field-programmable gate arrays (FPGAs). Previously, it was standard practice to downlink the radar-return data to a ground station for postprocessing a costly practice that prevents the nearly-real-time use of the data for automated targeting. In principle, the onboard processing could be performed by a system of about 20 personal- computer-type microprocessors; relative to such a system, the present FPGA-based processor is much smaller and consumes much less power. Alternatively, the onboard processing could be performed by an application-specific integrated circuit (ASIC), but in comparison with an ASIC implementation, the present FPGA implementation offers the advantages of (1) greater flexibility for research applications like the present one and (2) lower cost in the small production volumes typical of research applications. The generation and processing of signals in the airborne precipitation measuring radar system in question involves the following especially notable steps: The system utilizes a total of four channels two carrier frequencies and two polarizations at each frequency. The system uses pulse compression: that is, the transmitted pulse is spread out in time and the received echo of the pulse is processed with a matched filter to despread it. The return signal is band-limited and digitally demodulated to a complex baseband signal that, for each pulse, comprises a large number of samples. Each complex pair of samples (denoted a range gate in radar terminology) is associated with a numerical index that corresponds to a specific time offset from the beginning of the radar pulse, so that each such pair represents the energy reflected from a specific range. This energy and the average echo power are computed. The phase of each range bin is compared to the previous echo by complex conjugate multiplication to obtain the mean Doppler shift (and hence the mean and variance of the velocity of precipitation) of the echo at that range.

Berkun, Andrew↗

NASA NTRS2004

T/R module development for large aperture L-band phased array

This paper describes a transmit / receive (T/R) module for a large L-band space based radar active phased array being developed at JPL. Electrical performance and construction techniques are described, with emphasis on the former. The T/R modules have a bandwidth of more than 80 MHz centered at 1260MHz and support dual, switched polarizations. Phase and amplitude are controlled by a 6-bit phase shifter and a 6-bit attenuator, respectively. The transmitter power amplifier generates 2.4 W into a nominal 50 ohm load with 36% overall efficiency. The receiver noise figure is 4.4 dB including all front-end losses. The module weighs 32 g and has a footprint of 8 cm x 4.5 cm. Fourteen of these T/R modules were fabricated at the JPL Pick-and-Place Facility and were tested using a computer-controlled measurement facility developed at JPL. Calibrated performance of this set of T/R modules is presented and shows good agreement with design predictions.

transmit / receive (T/R) module↗