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Avizienis, A.

Publications and source records attributed to Avizienis, A..

17 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS1986

The UCLA Design Diversity Experiment (DEDIX) system: A distributed testbed for multiple-version software

To establish a long-term research facility for experimental investigations of design diversity as a means of achieving fault-tolerant systems, a distributed testbed for multiple-version software was designed. It is part of a local network, which utilizes the Locus distributed operating system to operate a set of 20 VAX 11/750 computers. It is used in experiments to measure the efficacy of design diversity and to investigate reliability increases under large-scale, controlled experimental conditions.

Avizienis, A.↗
NASA NTRS1986

Software fault-tolerance by design diversity DEDIX: A tool for experiments

The use of multiple versions of a computer program, independently designed from a common specification, to reduce the effects of an error is discussed. If these versions are designed by independent programming teams, it is expected that a fault in one version will not have the same behavior as any fault in the other versions. Since the errors in the output of the versions are different and uncorrelated, it is possible to run the versions concurrently, cross-check their results at prespecified points, and mask errors. A DEsign DIversity eXperiments (DEDIX) testbed was implemented to study the influence of common mode errors which can result in a failure of the entire system. The layered design of DEDIX and its decision algorithm are described.

Avizienis, A.↗
NASA NTRS1978

Fault-tolerance - The survival attribute of digital systems

Fault-tolerance is the architectural attribute of a digital system that keeps the logic machine doing its specified tasks when its host, the physical system, suffers various kinds of failures of its components. A more general concept of fault-tolerance also includes human mistakes committed during software and hardware implementation and during man/machine interaction among the causes of faults that are to be tolerated by the logic machine. This paper discusses the concept of fault-tolerance, the reasons for its inclusion in digital system architecture, and the methods of its implementation. A chronological view of the evolution of fault-tolerant systems and an outline of some goals for its further development conclude the presentation.

Avizienis, A.↗
NASA NTRS1978

A study of standard building blocks for the design of fault-tolerant distributed computer systems

This paper presents the results of a study that has established a standard set of four semiconductor VLSI building-block circuits. These circuits can be assembled with off-the-shelf microprocessors and semiconductor memory modules into fault-tolerant distributed computer configurations. The resulting multi-computer architecture uses self-checking computer modules backed up by a limited number of spares. A redundant bus system is employed for communication between computer modules.

Rennels, D. A.↗
NASA NTRS1973

Arithmetic algorithms for error-coded operands.

Arithmetic algorithms for separate and nonseparate codes are considered. The nonseparate AN code is formed when an uncoded operand X is multiplied by the check modulus A to give the coded operand AX. The separate codes are the residue code, and the inverse-residue code, which has significant advantages in fault detection of repeated-use faults. A set of algorithms for low-cost AN-coded operands is discussed together with questions of their implementation in a byte-organized arithmetic processor. Algorithms for inverse-residue coded operands of the STAR computer are also examined.

Avizienis, A.↗
NASA NTRS1972

Fault-tolerance experiments with the JPL STAR computer.

Results of fault-tolerance experiments performed using an experimental computer with dynamic (standby) redundancy, including replaceable subsystems and a 'program rollback' provision to eliminate transient-caused errors. After a brief review of the specification of fault-tolerance with respect to transient faults, including a description of the method of injection of transient faults in software and system tests, fault-tolerance experiments carried out with this computer with regard to the determination of fault classes, software verification, system verification, and recovery stability are summarized. A test and repair processor is described which constitutes a special monitor unit of the computer and is used to obtain information for fault detection in the other subsystems of the computer and to ensure that proper recovery occurs when a fault is detected.

Avizienis, A.↗
NASA NTRS1971

Arithmetic error codes - Cost and effectiveness studies for application in digital system design.

The application of error-detecting or error-correcting codes in digital computer design requires studies of cost and effectiveness tradeoffs to supplement the knowledge of their theoretical properties. General criteria for cost and effectiveness studies of error codes are developed, and results are presented for arithmetic error codes with the low-cost check modulus 2 super a - 1. Both separate (residue) and nonseparate (AN) codes are considered. The class of multiple arithmetic error codes is developed as an extension of low-cost single codes.

Avizienis, A.↗